Methods of fabricating isolation regions of semiconductor devices and structures thereof

• US 8,936,995 B2
• Filed: 03/01/2006
• Issued: 01/20/2015
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin, Culmsee, Marcus, Stapelmann, Chris, Hampp, Roland, Hong, Bee Kim
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US11/365,226
• Publication Number:
  US 20070205489A1
• Time in Patent Office: 3,247 Days
• Field of Search: 438/242, 438/700, 438268-274, 438221-224, 438/296, 438359-361, 438424-438, 438761-763, 257/118, 257/244, 257328-333, 257/466, 257/594, 257E21546-E2155, 257510-513
• US Class Current: 438/424
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a pad oxide over a workpiece;

forming a pad nitride over the pad oxide;

forming at least one trench in the pad nitride, the pad oxide and the workpiece, the at least one trench comprising sidewalls, a bottom surface, a lower portion, and an upper portion;

forming a first oxide liner over the sidewalls and the bottom surface of the at least one trench and not over a top surface of the pad nitride;

forming a second oxide liner directly on the first oxide liner and over the top surface of the pad nitride, the second oxide liner formed with a different process than the first oxide liner;

forming a nitride liner on a top surface of the second oxide liner;

filling the lower portion of the at least one trench with a first insulating material;

etching the nitride liner from the upper portion of the at least one trench after filling the lower portion of the at least one trench with the first insulating material;

filling the upper portion of the at least one trench with a second insulating material, the second insulating material comprising a different material than the first insulating material or the second insulating material being deposited using a different deposition method than the first insulating material, wherein the second insulating material is in physical contact with the nitride liner and with an upper portion of the top surface of the second oxide liner, wherein the first oxide liner, the second oxide liner, the nitride liner, the first insulating material, and the second insulating material in the at least one trench form an isolation region of the semiconductor device; and

removing the pad nitride, wherein the second oxide liner and the second insulating material extend above the workpiece by an amount greater than a thickness of the pad oxide.

2. The method according to claim 1, wherein filling the lower portion of the at least one trench with the first insulating material comprises:

depositing the first insulating material over the top surface of the pad nitride and entirely filling the at least one trench; and

removing the first insulating material from the upper portion of the at least one trench.

3. The method according to claim 1, wherein sidewalls of a portion of the second oxide liner and the second insulating material that extends above the workpiece are tapered inwardly toward the second insulating material.

4. The method according to claim 1, wherein the the second oxide liner and the second insulating material extend above the workpiece by about 30 nm.

23. The method according to claim 1, wherein filling the upper portion of the at least one trench comprises filling about ¼

or less of a total depth of the at least one trench.

24. The method according to claim 1, wherein an aspect ratio of the at least one trench is at least 5:

1 depth to width.

25. The method according to claim 1, wherein forming the second oxide liner comprises depositing tetra ethyl oxysilane using a sub-atmospheric chemical vapor deposition.

26. The method according to claim 1, wherein forming the nitride liner comprises using low pressure chemical vapor deposition.

5. A method of forming an isolation region of a semiconductor device, the method comprising:

forming a pad oxide over a workpiece;

forming a pad nitride over the pad oxide;

forming at least one trench in the pad nitride, the pad oxide, and the workpiece, the at least one trench having a lower portion and an upper portion, the at least one trench having sidewalls and a bottom surface;

depositing a first oxide liner over the sidewalls and on the bottom surface;

depositing a second oxide liner directly on a top surface of the first oxide liner, the second oxide liner disposed on top surfaces and sidewalls of the pad nitride;

depositing a nitride liner on a top surface of the second oxide liner;

forming a first insulating material in the lower portion of the at least one trench, the first insulating material disposed on the nitride liner;

forming a second insulating material in the upper portion of the at least one trench, the second insulating material physically contacting the nitride liner and the second oxide liner, wherein the first oxide liner, the second oxide liner, the nitride liner, the first insulating material, and the second insulating material form the isolation region of the semiconductor device; and

removing the pad nitride, wherein the second oxide liner and the second insulating material extend above the workpiece by an amount greater than a thickness of the pad oxide.

6. The method according to claim 5, wherein before forming the second insulating material in the upper portion of the at least one trench, etching the nitride liner from the upper portion of the at least one trench.

7. The method according to claim 5, wherein depositing the nitride liner comprises depositing about 4 nm or less of silicon nitride.

8. The method according to claim 5, wherein depositing the first oxide liner comprises oxidizing the sidewalls and bottom surface of the at least one trench.

9. The method according to claim 8, wherein oxidizing the sidewalls and bottom surface of the at least one trench within the workpiece comprises forming about 5 nm or less of silicon dioxide.

10. The method according to claim 5, wherein depositing the second oxide liner comprises depositing about 10 nm or less of silicon dioxide or tetra ethyl oxysilane (TEOS).

11. The method according to claim 5, wherein forming the first insulating material comprises forming spin-on glass (SOG) or silicon dioxide.

12. The method according to claim 5, wherein forming the first insulating material comprises depositing a material comprising a liquid when deposited.

13. The method according to claim 5, wherein forming the second insulating material comprises forming silicon dioxide, tetra ethyl oxysilane (TEOS), or high density plasma (HDP) oxide.

27. The method according to claim 5, wherein forming the second insulating material in the upper portion of the at least one trench comprises filling about ¼

or less of a total depth of the at least one trench.

28. The method according to claim 5, wherein an aspect ratio of the at least one trench is at least 5:

1 depth to width.

29. The method according to claim 5, wherein depositing the second oxide liner comprises depositing tetra ethyl oxysilane using a sub-atmospheric chemical vapor deposition.

30. The method according to claim 5, wherein depositing the nitride liner comprises using low pressure chemical vapor deposition.

14. A method of forming an isolation region of a semiconductor device, the method comprising:

forming a pad oxide over a top surface of a workpiece;

forming a pad nitride over the pad oxide;

forming at least one trench in the pad nitride, pad oxide and the workpiece, the at least one trench comprising sidewalls, a bottom surface, a lower portion, and an upper portion, wherein a first oxide liner is disposed on the sidewalls of the trench in the workpiece;

depositing a second oxide liner directly on the first oxide liner;

forming a nitride liner over the second oxide liner in the lower portion of the at least one trench;

filling the lower portion of the at least one trench with a first insulating material;

filling the upper portion of the at least one trench with a second insulating material, wherein the second insulating material is directly attached to the nitride liner and the second oxide liner;

removing the pad nitride from over the workpiece; and

removing a portion of the second insulating material from over the top surface of the workpiece, wherein after removing the portion of the second insulating material from over the top surface of the workpiece, the second oxide liner and the second insulating material are at least coplanar with the top surface of the workpiece, and wherein the second oxide liner, the nitride liner, the first insulating material, and the second insulating material form the isolation region of the semiconductor device, wherein the second oxide liner and the second insulating material extend above the workpiece by an amount greater than a thickness of the pad oxide.

15. The method according to claim 14, further comprising forming at least two active areas in the workpiece, wherein forming the at least one trench comprises forming a trench between the at least two active areas, wherein the isolation region provides isolation between the at least two active areas.

16. The method according to claim 15, wherein forming the at least two active areas in the workpiece comprises forming transistors, complementary metal oxide semiconductor (CMOS) devices, memory devices, logic devices, power devices, circuitry components, groups of circuitry components, or combinations thereof.

17. The method according to claim 14, wherein the isolation region comprises a shallow trench isolation (STI) region, a deep trench (DT) isolation region, or a combination of an STI region and a DT isolation region.

18. The method according to claim 14, wherein the upper portion of the at least one trench extends below the top surface of the workpiece by about 10 nm or greater.

19. The method according to claim 14, wherein filling the upper portion of the at least one trench comprises filling about ¼

or less of a total depth of the at least one trench.

20. The method according to claim 14, wherein an aspect ratio of the at least one trench is at least 5:

1 depth to width.

21. The method according to claim 14, wherein depositing the second oxide liner comprises depositing tetra ethyl oxysilane using a sub-atmospheric chemical vapor deposition.

22. The method according to claim 14, wherein forming the nitride liner comprises using low pressure chemical vapor deposition.