Striped on-chip inductor

• US 8,937,355 B2
• Filed: 05/11/2012
• Issued: 01/20/2015
• Est. Priority Date: 09/29/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cho, Choongyeun, Kim, Daeik, Kim, Jonghae, Kim, Moon J., Plouchart, Jean-Olivier, Trzcinski, Robert E.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/469,464
• Publication Number:
  US 20120223411A1
• Time in Patent Office: 984 Days
• Field of Search: 257/531, 336/223, 700/121
• US Class Current: 257/351
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Claims

1. A sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port;

the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap;

wherein the plurality of line widths, cross-sectional areas and spacing gaps are a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps formed to comply with the Chemical Mechanical Planarization metal ratio rule; and

wherein each of the lines have interior sidewalls in gap regions, the interior sidewalls each having interior sidewall heights, and wherein a sum of the spacing gaps is less than a sum of the interior sidewall heights.

2. The inductor of claim 1 wherein the plurality of line widths, cross-sectional areas and spacing gaps define a metal density ratio of 80% metal to 20% dielectric surface.

3. The inductor of claim 1 wherein the plurality of line widths, cross-sectional areas and spacing gaps are constant over a total inductor length.

4. The inductor of claim 1 wherein the inductor is formed in a top Chemical Mechanical Planarization metal layer of a complementary metal oxide semiconductor configured for 10 GHz radio frequencies.

5. The inductor of claim 1 wherein each line width is greater than or equal to about 0.8 microns and less than or equal to about 8 microns, and wherein each spacing gap is greater than or equal to about 0.8 microns.

6. The inductor of claim 1 wherein the plurality of lines have progressively larger line widths from a first innermost line to a last outermost line.

7. The inductor of claim 1 wherein the plurality of lines further comprises a plurality of connector lines, each connector line connecting at least two of the spaced parallel lines.