Contact formation for ultra-scaled devices

• US 8,937,359 B2
• Filed: 05/15/2013
• Issued: 01/20/2015
• Est. Priority Date: 05/15/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Xie, Ruilong, Ponoth, Shom, Horak, David V., Pranatharthiharan, Balasubramanian
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US13/894,513
• Publication Number:
  US 20140339629A1
• Time in Patent Office: 615 Days
• Field of Search: 257/382, 257/401, 257/E29.052, 438/284, 438/299
• US Class Current: 257/401
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

Claims

1. A method of forming a device, the method comprising:

forming a gate transistor over a substrate;

forming a source/drain (S/D) contact over a trench-silicide (TS) layer formed adjacent the gate transistor; and

forming a gate contact over the gate transistor, wherein at least a portion of the gate contact is positioned over the TS layer.

2. The method according to claim 1, further comprising forming a set of fins in an active region over the substrate.

3. The method according to claim 1, further comprising forming a plurality of gate transistors over the substrate by:

providing a set of gate structures;

removing a metal layer to form a gate recess for each of the set of gate structures;

forming a spacer protection layer over the set of gate structures;

forming a capping layer over the set of gate structures;

forming a dielectric layer over the capping layer; and

removing the TS layer and the dielectric layer over the set of gate structures.

4. The method according to claim 3, the forming the plurality of gate transistors further comprising:

forming a recess within the TS layer adjacent one or more of the set of gate structures;

forming an interlayer dielectric (ILD) over the set of gate structures;

etching the ILD to form an opening for the S/D contact;

forming an organic dielectric layer (ODL) within the opening for the S/D contact;

etching the ILD to form an opening for the gate contact;

removing the ODL; and

depositing a metal material over the set of gate structures.

5. The method according to claim 4, further comprising forming an etch stop layer over the set of gate structures following the formation of the recess within the TS layer adjacent one or more of the set of gate structures.

6. The method according to claim 3, the forming the plurality of gate transistors further comprising:

forming an interlayer dielectric layer (IDL) over the set of gate structures;

etching the IDL to form an opening for the S/D contact;

depositing a metal material into the opening for the S/D contact to form the S/D contact;

forming another IDL layer over the S/D contact;

etching the ILD and the another IDL to form an opening for the gate contact;

forming a recess within the TS layer adjacent one of the set of gate structures;

forming an atomic layer deposition (ALD) oxide fill over the set of gate structures;

etching the ALD oxide fill over the set of gate structures without removing a portion of the ALD oxide fill formed within the recess within the TS layer;

forming a set of spacers for the gate contact;

removing the capping layer formed within the opening for the gate contact; and

depositing a metal layer over the set of gate structures.

7. The method according to claim 1, wherein the TS layer is one of:

entirely recessed beneath the S/D contact, and partially recessed beneath the S/D contact below the portion of the gate contact positioned over the TS layer.

8. The method according to claim 1, further comprising forming a source-trench isolation region over the substrate.

9. A method for forming contacts in an ultra-scaled semiconductor device, the method comprising:

forming a gate transistor over a substrate;

forming a source/drain (S/D) contact over a trench-silicide (TS) layer formed adjacent the gate transistor; and

forming a gate contact over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer.

10. The method according to claim 9, further comprising forming a set of fins in an active region over the substrate.

11. The method according to claim 9, further comprising forming a plurality of gate transistors over the substrate by:

providing a set of gate structures;

removing a metal layer to form a gate recess for each of the set of gate structures;

forming a spacer protection layer over the set of gate structures;

forming a capping layer over the set of gate structures;

forming a dielectric layer over the capping layer; and

removing the TS layer and the dielectric layer over the set of gate structures.

12. The method according to claim 11, the forming the plurality of gate transistors further comprising:

forming a recess within the TS layer adjacent one or more of the set of gate structures;

forming an interlayer dielectric (ILD) over the set of gate structures;

etching the ILD to form an opening for the S/D contact;

forming an organic dielectric layer (ODL) within the opening for the S/D contact;

etching the ILD to form an opening for the gate contact;

removing the ODL; and

depositing a metal material over the set of gate structures.

13. The method according to claim 12, further comprising forming an etch stop layer over the set of gate structures following the formation of the recess within the TS layer adjacent one or more of the set of gate structures.

14. The method according to claim 11, the forming the plurality of gate transistors further comprising:

forming an interlayer dielectric layer (IDL) over the set of gate structures;

etching the IDL to form an opening for the S/D contact;

depositing a metal material into the opening for the S/D contact to form the S/D contact;

forming another IDL layer over the S/D contact;

etching the ILD and the another IDL to form an opening for the gate contact;

forming a recess within the TS layer adjacent one of the set of gate structures;

forming an atomic layer deposition (ALD) oxide fill over the set of gate structures;

etching the ALD oxide fill over the set of gate structures without removing a portion of the ALD oxide fill formed within the recess within the TS layer;

forming a set of spacers for the gate contact;

removing the capping layer formed within the opening for the gate contact; and

depositing a metal layer over the set of gate structures.

15. The method according to claim 9, wherein the TS layer is one of:

entirely recessed beneath the S/D contact, and partially recessed beneath the S/D contact below the portion of the gate contact positioned over the TS layer.

16. The method according to claim 9, further comprising forming a source-trench isolation region over the substrate.

17. A semiconductor device comprising:

a replacement metal gate (RMG) transistor formed over a substrate;

a source/drain (S/D) contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor; and

a gate contact formed over the RMG transistor, wherein at least a portion of the gate contact is vertically aligned over the TS layer.

18. The device according to claim 17, further comprising a plurality of RMG transistors formed over the substrate, the plurality of RMG transistors including:

a set of gate structures formed over a substrate;

a metal layer within a gate recess of each of the set of gate structures; and

an interlayer dielectric formed over the set of gate structures.

19. The device according to claim 18, the plurality of gate transistors further comprising:

a recess within the TS layer adjacent one of the set of gate structures;

an atomic layer deposition (ALD) oxide fill within the recess; and

a set of spacers for the gate contact.

20. The device according to claim 17, wherein the TS layer is one of:

entirely recessed beneath the S/D contact, and partially recessed beneath the S/D contact below the portion of the gate contact positioned over the TS layer.