Clock monitor
First Claim
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1. A circuit, including:
- a clock monitoring circuit configured and arranged to receive first and second clock signals generated in respective clock domains, the clock monitoring circuit including;
a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal and output a first count value indicating the number of counted clock cycles; and
a first threshold comparator circuit configured and arranged to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of a first expected range.
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Abstract
A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.
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Citations
20 Claims
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1. A circuit, including:
a clock monitoring circuit configured and arranged to receive first and second clock signals generated in respective clock domains, the clock monitoring circuit including; a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal and output a first count value indicating the number of counted clock cycles; and a first threshold comparator circuit configured and arranged to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of a first expected range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for monitoring a first clock signal, comprising:
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counting clock cycles of the first clock signal for a first period of time delineated by clock cycles of a second clock signal, wherein the first and second clock signals are derived from different clock sources; and in response to the counted number of clock cycles falling outside of an expected range, defined by an upper threshold number and a lower threshold number, generating an error signal. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method for monitoring a first clock signal, comprising:
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selecting a first number of clock cycles; determining a range of clock cycles expected to be observed in the first clock signal within the period of time; simulating one or more errors in the first clock signal; and monitoring the first clock signal for errors by performing operations including; counting clock cycles of the first clock signal for a period of time defined by the first number of clock cycles in a second clock signal, wherein the first and second clock signals are derived from different clock sources; and in response to the counted number of clock cycles falling outside of the range, generating an error signal. - View Dependent Claims (20)
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Specification