Improving receiver performance in a communication network

• US 8,938,040 B2
• Filed: 10/05/2007
• Issued: 01/20/2015
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Cohda Wireless Pty Ltd.
• Original Assignee: Cohda Wireless Pty Ltd.
• Inventors: Alexander, Paul Dean, Haley, David Victor Lawrie, Buetefuer, John Lawrence, Grant, Alexander James, Sutton, Joshua Charles, Suter, Martin, Gray, Paul Kingsley, Pham, Phuc Ngoc
• Primary Examiner(s): Lugo, David B.
• Application Number:
  US12/444,279
• Publication Number:
  US 20100091920A1
• Time in Patent Office: 2,664 Days
• Field of Search: 375/229, 375/230, 375/232, 375/316, 375/340, 375/346, 375/349, 375/350
• US Class Current: 375/350
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0048 in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder for spatial equalizer H04L25/03286
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 25/0202 Channel estimation
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 25/022 of frequency response
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 25/03318 Provision of soft decisions
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

Methods and apparatus are described for improving receiver performance in a multicarrier communication network in which an encoded symbol (250) is transmitted over a transmission channel (20) in the communications system. A model of the transmission channel (20) is estimated (718, 760), said model characterizing an effect of intercarrier interference on at least one carrier in the multicarrier system. The received symbol (250) is decoded (720, 762) using the estimated model to remove a predicted effect of intercarrier interference. A pre-processor (40) is also described for operation in conjunction with a communications receiver (30) in the network. The pre-processor (40) includes a channel estimator (42) operable to estimate at least one feature of the communication channel based on a received signal. The pre-processor (40) modifies the received signal dependent on the at least one estimated feature and provides the modified signal to the communications receiver (30).

Claims

1. A pre-processor paired in use with a communications receiver, the receiver configured to receive a signal including encoded data and to extract a decoded estimate of the data, the pre-processor comprising:

an input operable to receive an input signal that is transmitted via a communication channel to the paired pre-processor and communications receiver, the input signal including first encoded data;

a channel estimator operable to estimate at least one feature of the communication channel based on the input signal and a feedback signal;

a signal modifier operable to modify the input signal dependent on the at least one estimated feature to result in a modified signal including second encoded data related to and different from the first encoded data, the signal modifier including a forward error correction (FEC) unit for deriving the feedback signal provided to the channel estimator; and

an output for providing the modified signal to the communications receiver, wherein the channel estimator and the signal modifier operate without feedback from the communications receiver.

2. A pre-processor according to claim 1 wherein said signal modifier comprises a time-domain filter.

3. A pre-processor according to claim 2 further comprising:

a coefficient calculator operable to determine one or more coefficients of said time-domain filter based on an output of said channel estimator.

4. A pre-processor according to claim 1 wherein said signal modifier modifies the input signal in the frequency domain.

5. A pre-processor according to claim 4 wherein said signal modifier comprises:

a combiner operable to combine the input signal and an output of said channel estimator.

6. A pre-processor according to claim 5 wherein said combiner is selected from the group consisting of:

a maximum ratio combiner (MRC);

a zero forcing combiner; and

a minimum mean square error combiner.

7. A pre-processor according to claim 5 wherein said channel estimator estimates the at least one feature dependent on an output of said combiner.

8. A pre-processor according to claim 5 wherein said signal modifier further comprises a modulation unit and wherein said channel estimator is driven with an output of said combiner that is demodulated and re-modulated.

9. A pre-processor according to claim 8 wherein said channel estimator is driven with an output of said combiner that is demodulated, FEC decoded, FEC re-encoded and re-modulated.

10. A pre-processor according to claim 1 wherein the communications receiver is an RF/PHY/MAC receiver and wherein, in use, said pre-processor operates between an antenna and the communications receiver.

11. A pre-processor according to claim 10 wherein said pre-processor is operable as a bridge that receives the input signal from one or more RF circuits and retransmits an output signal to the PHY/MAC communications receiver.

12. A pre-processor according to claim 1 further comprising one or more RF circuits.

13. A pre-processor according to claim 12 wherein, in use, said pre-processor operates between one or more antennas and the communications receiver.

14. A pre-processor according to claim 1 wherein, in use, said pre-processor operates between one or more RF circuits and the communications receiver.

15. A pre-processor according to claim 14 operable to bypass an acquisition circuit of the communications receiver.

16. A pre-processor according to claim 14 wherein said pre-processor processes a status and a control signal from the RF circuit and said output outputs the processed status and control signals.

17. A pre-processor according to claim 1 wherein the pre-processor is operable as a PHY module.

18. A pre-processor according to claim 17 and operable to bypass a PHY module of the communications receiver.

19. A pre-processor according to claim 1 wherein the pre-processor is operable with IEEE 802.11 compliant receivers.

20. A pre-processor according to claim 1 having a bypass mode in which the input signal passes from said input to said output with substantially no modification.

21. A pre-processor according to claim 1 further comprising:

an acquisition circuit that utilises two autocorrelations of different lengths.

22. A pre-processor according to claim 1 further comprising:

data storage storing at least one preamble for inclusion in the modified signal provided to the communications receiver.

23. A pre-processor according to claim 1 wherein at least one preamble and optionally some data symbols are passed from said input to said output.

24. A pre-processor according to claim 1 further comprising a filter for filtering a signal preamble for inclusion in the modified signal provided to the communications receiver.

25. A pre-processor according to claim 1 wherein a part of a preamble is modified or deleted before inclusion in the modified signal.

26. A pre-processor according to claim 1 wherein said output outputs a short preamble if the input signal is detected by said input.

27. A pre-processor according to claim 26 wherein said output outputs a long preamble once a timing of the input signal is acquired.

28. A pre-processor according to claim 27 wherein said output outputs the short preamble repeatedly and then outputs the long preamble once timing is acquired.

29. A pre-processor according to claim 1 wherein said input is operable to receive a plurality of input signals.

30. A pre-processor according to claim 29 comprising a selector operable to select an input signal from the plurality of input signals.

31. A pre-processor according to claim 29 wherein said channel estimator and said signal modifier operate on the plurality of input signals.

32. A pre-processor according to claim 1 wherein said signal modifier is arranged to modify the input signal dependent on a predefined capability of the communications receiver.

33. A pre-processor according to claim 1, wherein the pre-processor is arranged to expand a range of communication channels with which the communications receiver is operable.

34. A communications system comprising at least one pre-processor-enabled node comprising:

a pre-processor according to claim 1; and

the communications receiver that receives a modified signal from the paired pre-processor.

35. A communications system according to claim 34 further comprising at least one non-pre-processor-enabled node comprising a communications receiver that receives an input signal directly.

36. A communications system according to claim 34 wherein the communications system is an IEEE 802.11 network, the system comprising a delay compensator selected from the group consisting of:

a delay compensator that compensates for delay in a Pre-Processor enabled node by increasing the Coverage Class;

a delay compensator that compensates for delay in a Pre-Processor enabled node by decreasing short interframe space (SIFS) time of an IEEE 802.11 MAC/PHY;

a delay compensator that compensates for delay in a Pre-Processor enabled node by increasing SIFS time to point control function interframe space (PIFS) time;

a delay compensator that compensates for delay in a Pre-Processor enabled node by outputting signals at a higher data rate from the Pre-Processor than a data rate of the input signal received from the channel; and

a delay compensator that compensates for delay in a Pre-Processor enabled node by asserting a clear channel assessment (CCA) signal of an IEEE 802.11 MAC/PHY early.

37. The communications system of claim 34 wherein the input signal and the modified signal share substantially the same signal modulation format and multiplexing scheme.

38. The pre-processor of claim 1 wherein the feedback signal includes a time-domain feedback signal and a frequency domain feedback signal.

39. The pre-processor of claim 1 wherein the FEC unit is configured to perform forward error correction in the frequency domain.

40. The pre-processor of claim 1 wherein the input signal and the modified signal share substantially the same signal modulation format and multiplexing scheme.

41. A method of pre-processing a signal in a pre-processor paired in use with a communications receiver, the receiver configured to receive a signal including encoded data and to extract a decoded estimate of the data, said method comprising:

receiving an input signal that is transmitted via a communication channel to the paired pre-processor and communications receiver, the input signal including first encoded data;

estimating at least one feature of the communication channel based on the input signal and a feedback signal, wherein the feedback signal is derivable from a forward error correction (FEC) unit;

modifying the input signal dependent on the at least one estimated feature and a predefined capability of the communications receiver to result in a modified signal including second encoded related to and different from the first encoded data, wherein said estimating and said modifying are performed without feedback from the communications receiver; and

providing the modified signal to the communications receiver.

42. The method of claim 41 wherein the input signal and the modified signal share substantially the same signal modulation format and multiplexing scheme.

43. A computer program product comprising machine-readable program code recorded on a non-transitory machine-readable recording medium, for controlling the operation of a data processing apparatus on which the program code executes to perform a method of pre-processing a signal in a pre-processor paired in use with a communications receiver, the receiver configured to receive a signal including encoded data and to extract a decoded estimate of the data, said method comprising:

receiving an input signal that is transmitted via a communication channel to the paired pre-processor and communications receiver, the input signal including first encoded data;

estimating at least one feature of the communication channel based on the input signal and a feedback signal, wherein the feedback signal is derivable from a forward error correction (FEC) unit;

modifying the input signal dependent on the at least one estimated feature and a predefined capability of the communications receiver to result in a modified signal including second encoded data related to and different from the first encoded data, wherein said estimating and said modifying are performed without feedback from the communications receiver; and

providing the modified signal to the communications receiver.

44. The computer program product of claim 43 wherein the input signal and the modified signal share substantially the same signal modulation format and multiplexing scheme.