Synchronization modules for programmable hardware and use

• US 8,938,716 B2
• Filed: 07/03/2014
• Issued: 01/20/2015
• Est. Priority Date: 02/17/2012
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Graf, Christopher F., Brown, Ryan H., Baker, Daniel J., DeVoe, Matthew J., Nagarajan, Sarvesh V.
• Primary Examiner(s): Das, Chameli
• Application Number:
  US14/323,479
• Publication Number:
  US 20140317599A1
• Time in Patent Office: 201 Days
• Field of Search: None
• US Class Current: 717/121
• CPC Class Codes: G05B 19/05 Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• CPC Class Codes: G06F 11/3696 Methods or tools to render software testable
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management

Abstract

Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Claims

1. A method for customizing a test instrument, wherein the test instrument comprises at least a first device with a first programmable hardware element (PHE) and a second device with a second PHE, the method comprising:

storing first and second synchronization modules respectively comprising code for implementation on the first and second PHEs, wherein the first and second synchronization modules implement first and second synchronization functionality, respectively, and wherein the first and second synchronization modules each includes a standard interface for interacting with other code;

storing first and second user-created code which implement first and second functions, respectively;

associating, in response to user input, the first and second synchronization modules with the first and second user-created code, respectively, wherein the first and second user-created code are respectively configured to interact with the first and second synchronization modules using the standard interface, and wherein the standard interface allows swapping out either of the synchronization modules with another synchronization module without requiring modification of the associated user-created code;

generating first and second hardware descriptions based respectively on the first synchronization module and first user-created code, and the second synchronization module and second user-created code, wherein the first and second hardware descriptions implement the first and second synchronization functionalities and functions, respectively, such that deploying the first and second hardware descriptions to the first and second PHEs, respectively, configures the first and second PHEs to perform the first and second functions together in synchrony.

2. The method of claim 1, wherein the first user-created code and the second user-created code utilize a plurality of custom triggers, wherein each custom trigger is invoked and received using the first and second synchronization modules.

3. The method of claim 1, wherein the first and second synchronization modules are instantiations of a common synchronization module.

4. The method of claim 1, wherein the first and second synchronization modules are different.

5. The method of claim 1, wherein the first and second synchronization modules and the first and second user-created code comprise graphical programs.

6. The method of claim 5, wherein said associating the first and second synchronization modules with the first and second user-created code, respectively, comprises connecting, in a graphical program, the first and synchronization modules to the first and second user-created code, respectively.

7. The method of claim 1, further comprising:

providing a library of synchronization modules; and

receiving user input selecting the first and second synchronization modules from the library of synchronization modules.

8. The method of claim 1, further comprising:

providing a graphical user interface (GUI) for configuring each of the first and second synchronization modules.

9. The method of claim 1, wherein the first and second synchronization modules comprise first and second synchronization module pairs, each pair comprising processor-side code and PHE-side code.

10. The method of claim 9, further comprising:

configuring the test instrument, wherein said configuring comprises configuring the first PHE according to the first hardware description and configuring the second PHE according to the second hardware description, wherein said configuring further comprises storing program instructions corresponding to the processor-side code in one or more memory mediums of the test instrument.

11. The method of claim 1, wherein the first synchronization module and the second synchronization module provide a first synchronization type for the first and second user-created code, wherein the method further comprises:

storing third and fourth synchronization modules, wherein the first and second synchronization modules implement first and second synchronization functionality, respectively; and

associating, in response to user input, the first user-created code with the third synchronization module and the second user-created code with the fourth synchronization module, wherein the third and fourth synchronization modules provide a second synchronization type for the first and second user-created code;

wherein said generating the first and second hardware descriptions are also based on the third and fourth synchronization modules, respectively; and

wherein the first and second synchronization modules, and the third and fourth synchronization modules, are configured to independently synchronize respective portions of the first and second user-created code.

12. A non-transitory computer accessible memory medium that stores program instructions for customizing a system, wherein the system comprises at least a first programmable hardware element (PHE) and a second PHE, wherein the program instructions are executable to:

create first and second programs for implementation on the first and second PHEs, respectively, comprising;

selecting and inserting, in response to user input, first and second synchronization modules into the first and second programs, respectively, wherein the first and second synchronization modules respectively comprise respective code implementing first and second synchronization functionality for implementation on the first and second PHEs, respectively, and wherein the first and second synchronization modules each includes a standard interface for interacting with other code;

creating, in response to user input, first and second user-created code which implements first and second functions, respectively; and

associating, in response to user input, the first and second synchronization modules with the first and second user-created code in the first and second programs, respectively, wherein the first and second user-created code are configured to interact with the first and second synchronization modules, respectively, using the standard interface, and wherein the standard interface allows swapping out either of the synchronization modules with another synchronization module without requiring modification of the associated user-created code; and

generate first and second hardware descriptions based respectively on the first synchronization module and first user-created code, and the second synchronization module and second user-created code, wherein the first and second hardware descriptions implement the first and synchronization functionalities and functions, respectively, such that deploying the first and second hardware descriptions to the first and second PHEs, respectively, configures the first and second PHEs to perform the first and second functions together in synchrony.

13. The non-transitory computer accessible memory medium of claim 12, wherein the system comprises a first device comprising the first PHE and a second device comprising the second PHE, and wherein the first user-created code is implemented on the first device and the second user-created code is implemented on the second device.

14. The non-transitory computer accessible memory medium of claim 12, wherein the program instructions are further executable to:

configure the first PHE according to the first hardware description; and

configure the second PHE according to the second hardware description;

wherein, during operation, the first PHE and the second PHE operate to communicate with each other to synchronize the first and second functions.

15. The non-transitory computer accessible memory medium of claim 12, wherein the first user-created code and the second user-created code utilize a plurality of custom triggers, and wherein each custom trigger is invoked and received using the first and second synchronization modules.

16. The non-transitory computer accessible memory medium of claim 12, wherein the first and second synchronization modules are instantiations of a common synchronization module.

17. The non-transitory computer accessible memory medium of claim 12, wherein the first and second synchronization modules and the first and second user-created code comprise graphical programs.

18. The non-transitory computer accessible memory medium of claim 17, wherein said associating the first and second synchronization modules with the first and second user-created code, respectively, comprises connecting, in a graphical program, the first and synchronization modules to the first and second user-created code, respectively.

19. The non-transitory computer accessible memory medium of claim 12, wherein the program instructions are further executable to:

provide a library of synchronization modules; and

receive user input selecting the first and second synchronization modules from the library of synchronization modules.

20. The non-transitory computer accessible memory medium of claim 12, wherein the first and second synchronization modules comprise first and second synchronization module pairs, each pair comprising processor-side code and PHE-side code.

21. The non-transitory computer accessible memory medium of claim 12, wherein the program instructions are further executable to:

configure the test instrument, wherein to configure the test instrument, the program instructions are further executable to;

configure the first PHE according to the first hardware description and configuring the second PHE according to the second hardware description; and

store program instructions corresponding to the processor-side code in one or more memory mediums of the test instrument.

22. The non-transitory computer accessible memory medium of claim 12, wherein the first synchronization module and the second synchronization module provide a first synchronization type for the first and second user-created code, wherein the program instructions are further executable to:

store third and fourth synchronization modules, wherein the first and second synchronization modules implement first and second synchronization functionality, respectively; and

associating, in response to user input, the first user-created code with the third synchronization module and the second user-created code with the fourth synchronization module, wherein the third and fourth synchronization modules provide a second synchronization type for the first and second user-created code;

wherein said generating the first and second hardware descriptions are also based on the third and fourth synchronization modules, respectively; and

wherein the first and second synchronization modules, and the third and fourth synchronization modules, are configured to independently synchronize respective portions of the first and second user-created code.

23. A method for customizing a test instrument, wherein the test instrument comprises at least a first device with a first programmable hardware element (PHE), comprising:

storing a first synchronization module comprising code for implementation on the first PHE of the first device, wherein the first synchronization module implements first synchronization functionality, and wherein the first synchronization module provides a standard interface for interacting with other code;

storing first user-created code which implements a first function;

associating, in response to user input, the first synchronization module with the first user-created code, wherein the first user-created code is configured to interact with the first synchronization module using the standard interface, and wherein the standard interface allows swapping out the first synchronization module with another synchronization module without requiring modification of the first user-created code; and

generating a first hardware description based on the first synchronization module and the associated first user-created code, wherein the first hardware description implements the first synchronization functionality and the first function such that deploying the first hardware description to the first PHE configures the first PHE to perform the first function in synchrony with operation of a second PHE, and wherein the second PHE is configured with a second synchronization module that implements second synchronization functionality and is associated with second user-created code that implements a second function.

24. A non-transitory computer accessible memory medium that stores program instructions for customizing a system, wherein the system comprises a first programmable hardware element (PHE), wherein the program instructions are executable to:

create a first program for implementation on the first PHE, comprising;

selecting and inserting, in response to user input, a first synchronization module into the first program, wherein the first synchronization module comprises code implementing first a synchronization functionality for implementation on the first PHE, and wherein the first synchronization module includes a standard interface for interacting with other code;

creating, in response to user input, first user-created code which implements a first function; and

associating, in response to user input, the first synchronization module with the first user-created code in the first program, wherein the first user-created code is configured to interact with the first synchronization module using the standard interface, and wherein the standard interface allows swapping out the first synchronization module with another synchronization module without requiring modification of the associated first user-created code; and

generate a first hardware description based on the first synchronization module and the first user-created code, wherein the first hardware description implements the first synchronization functionality and the first function such that deploying the first hardware description to the first PHE configures the first PHE to perform the first function in synchrony with operation of a second PHE, and wherein the second PHE is configured with a second synchronization module that implements second synchronization functionality and is associated with second user-created code that implements a second function.