Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

• US 8,940,581 B2
• Filed: 11/16/2011
• Issued: 01/27/2015
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Choon Kuan, Chong, Chin Hui, Corisis, David J.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/298,140
• Publication Number:
  US 20120187567A1
• Time in Patent Office: 1,168 Days
• Field of Search: 438/109, 438/118, 438/667, 438/108, 438/458, 257/E23.011, 257/E21.599
• US Class Current: 438/108
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/29005 Structure
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Claims

1. A method for manufacturing stacked microelectronic devices, the method comprising:

placing an attachment structure on a back side of a first microelectronic die, wherein the attachment structure includes a plurality of openings at least partially aligned with back side portions of electrically conductive through-substrate interconnects in the first die, and wherein the attachment structure further includes a plurality of conductive couplers formed in at least a portion of the openings and electrically coupled to corresponding through-substrate interconnects;

after placing the attachment structure on the back side of the first microelectronic die, contacting the attachment structure with a front side of a second microelectronic die;

joining the back side of the first die and the front side of the second die, wherein the first die is physically and electrically connected with the second die via the attachment structure; and

attaching a back side of the second die to a support member and electrically coupling the second die to the support member before joining the first and second dies.

2. The method of claim 1 wherein placing an attachment structure comprises attaching a dielectric adhesive film having a plurality of preformed openings to the back side of the first die.

3. The method of claim 2 wherein attaching a dielectric adhesive film comprises attaching a single, unitary piece of adhesive film that covers at least approximately all of the back side of the first die.

4. The method of claim 1 wherein the second die is attached and electrically coupled to the support member in a chip-on-board (COB) configuration with a plurality of wire bonds connecting first terminals at the front side of the second die with corresponding contacts on the support member, and further wherein:

joining the back side of the first die and the front side of the second die with the attachment structure includes (a) covering at least a portion of the wire bonds with the attachment structure, and (b) physically and electrically connecting the conductive couplers of the attachment structure to corresponding second terminals at the front side of the second die.

5. The method of claim 1 wherein the through-substrate interconnects are first through-substrate interconnects, and wherein the second die includes a plurality of second through-substrate interconnects, and further wherein:

joining the back side of the first die and the front side of the second die with the attachment structure includes physically and electrically coupling first through-substrate interconnects with second through-substrate interconnects via corresponding conductive couplers of the attachment structure.

6. The method of claim 1 wherein the attachment structure is formed at the back side of the first die and the conductive couplers are electrically coupled to internal active features of the first die before the first die is joined with the second die.

7. A method of processing a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and terminals electrically coupled to the integrated circuitry, the method comprising:

constructing a plurality of electrically conductive through-substrate interconnects extending at least partially through the semiconductor substrate and in contact with corresponding terminals;

disposing a connection structure on a back side of the semiconductor substrate, wherein the connection structure is a single, unitary structure covering at least approximately the entire back side of the semiconductor substrate and having a plurality of preformed apertures at least partially aligned with back side portions of the through-substrate interconnects; and

depositing conductive material into the apertures and forming a plurality of conductive couplers in contact with back side portions of the through-substrate interconnects.

8. The method of claim 7 wherein disposing a connection structure on a back side of the semiconductor substrate comprises applying a film-over-wire die attach film to the back side of the substrate, the film having a size and shape at least approximately identical to a size and shape of the semiconductor substrate.

9. The method of claim 7 wherein depositing conductive material into the apertures comprises applying a first layer of Cu onto the back side portions of the through-substrate interconnects, a second layer of Ni over at least a portion of the first layer of Cu, and a third layer of Au over at least a portion of the second layer of Cu, and wherein the first, second, and third layers are applied using a plating process.

10. The method of claim 7, further comprising removing material from a back side of the semiconductor substrate to thin the substrate after constructing the electrically conductive through-substrate interconnects and before disposing the connection structure on the back side of the semiconductor substrate.

11. A method of processing a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and terminals electrically coupled to the integrated circuitry, the method comprising:

constructing a plurality of electrically conductive through-substrate interconnects extending at least partially through the semiconductor substrate and in contact with corresponding terminals;

disposing a connection structure on a back side of the semiconductor substrate, the connection structure including a single, unitary structure covering at least approximately the entire back side of the semiconductor substrate and having a plurality of preformed apertures at least partially aligned with back side portions of the through-substrate interconnects;

depositing conductive material into the apertures and forming a plurality of conductive couplers in contact with back side portions of the through-substrate interconnects; and

singulating the semiconductor substrate after depositing the conductive material into the apertures.

12. A method for manufacturing stacked microelectronic devices, the method comprising:

placing an attachment structure on a back side of a first microelectronic die, wherein the attachment structure is a dielectric adhesive film including a plurality of preformed openings at least partially aligned with back side portions of electrically conductive through-substrate interconnects in the first die, and wherein the attachment structure further includes a plurality of conductive couplers formed in at least a portion of the openings and electrically coupled to corresponding through-substrate interconnects;

contacting the attachment structure with a front side of a second microelectronic die; and

joining the back side of the first die and the front side of the second die, wherein the first die is physically and electrically connected with the second die via the attachment structure.

13. A method of processing a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and terminals electrically coupled to the integrated circuitry, the method comprising:

constructing a plurality of electrically conductive through-substrate interconnects extending at least partially through the semiconductor substrate and in contact with corresponding terminals;

disposing a connection structure on a back side of the semiconductor substrate, the connection structure comprising a film-over-wire die attach film having a plurality of preformed apertures at least partially aligned with back side portions of the through-substrate interconnects, and wherein the die attach film has a size and shape at least approximately identical to a size and shape of the semiconductor substrate; and

depositing conductive material into the apertures and forming a plurality of conductive couplers in contact with back side portions of the through-substrate interconnects.