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Method of fabricating a high-voltage transistor with an extended drain structure

  • US 8,940,605 B2
  • Filed: 08/12/2011
  • Issued: 01/27/2015
  • Est. Priority Date: 09/07/2001
  • Status: Expired due to Fees
First Claim
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1. A method comprising:

  • forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls;

    covering the first and second sidewalls of each of the trenches with a dielectric material;

    forming first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from a top surface of the semiconductor substrate down to near a bottom of the mesa;

    forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source region from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the bottom of the mesa; and

    forming a trench gate within the dielectric material adjacent the body region, the trench gate being insulated from the body region and the first and second field plates.

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