Bonding method using porosified surfaces for making stacked structures

• US 8,940,616 B2
• Filed: 07/27/2012
• Issued: 01/27/2015
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Singapore Pte. Ltd. (Vanguard International Semiconductor Corporation)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Kotlanka, Rama Krishna, Kumar, Rakesh, Yelehanka, Pradeep, Chirayarikathuveedu Sankarapillai, Premachandran, Lin, Huamao
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Peterson, Erik T
• Application Number:
  US13/559,626
• Publication Number:
  US 20140030847A1
• Time in Patent Office: 914 Days
• Field of Search: 438455-459, 438/406, 438/409, 438/960, 438/15, 438/26, 438 50- 53, 438/67, 438/106, 438/107, 156/228, 422/502
• US Class Current: 438/455
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2201/0115 Porous silicon
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Claims

1. A method for bonding semiconductor surfaces comprising:

providing a first substrate with a first bonding region, wherein the first bonding region comprises a first bonding surface with a porosified region which is formed in the first substrate and is part of first substrate material;

providing a second substrate with a second bonding region having a second bonding surface, wherein the second bonding surface includes a second conductive contact comprising a TSV contact;

aligning the second conductive contact of the second bonding surface to be above and within the porosified region of the first bonding surface; and

bonding the second bonding surface with the second conductive contact to the first bonding surface with the porosified region by applying pressure at an elevated temperature.

2. The method of claim 1 wherein the porosified region comprises silicon, germanium or silicon germanium.

3. The method of claim 2 comprises forming the porosified region in the first bonding region, wherein forming the porosified region comprises stain etching or anodization.

4. The method of claim 1 comprises forming the porosified region in the first bonding region, wherein forming the porosified region comprises stain etching or anodization.

5. The method of claim 4 further comprises forming a first metal layer over the porosified region of the first bonding surface, wherein the porosified region causes the complete first metal layer to remain in direct contact with the porosified region after bonding.

6. The method of claim 5 further comprises forming a second metal layer over the second conductive contact, wherein the second metal layer bonds to the first metal layer in the first bonding region.

7. The method of claim 6 wherein the first and second metal layers comprise Titanium (Ti), Copper (Cu), Aluminum (Al) or a combination thereof.

8. The method of claim 6 wherein the first and second metal layers comprise sintered metal or metal nanowires or a combination thereof.

9. The method of claim 4 further comprises forming a second metal layer over the second conductive contact, wherein the second metal layer bonds to the porosified region of the first bonding surface.

10. The method of claim 9 wherein the second metal layer comprises Ti, Cu, Al or a combination thereof.

11. The method of claim 9 wherein bonding comprises eutectic bonding or thermo-compression bonding.

12. The method of claim 1 further comprises forming a first metal layer over the porosified region of the first bonding surface, wherein the porosified region causes the complete first metal layer to remain in direct contact with the porosified region after bonding.

13. The method of claim 12 further comprises forming a second metal layer over the second conductive contact, wherein the second metal layer bonds to the first metal layer in the first bonding region.

14. The method of claim 1 further comprises forming a getter layer over the second bonding surface.

15. The method of claim 1 further comprises forming a SAM layer over the first bonding region.

16. The method of claim 1 wherein bonding comprises eutectic bonding or thermo-compression bonding.

17. The method of claim 1 wherein:

the first substrate comprises a MEMS device; and

the second substrate comprises a CMOS device.

18. The method of claim 1 comprising providing an interconnect dielectric layer on the second substrate, wherein the interconnect dielectric layer surrounds the TSV contact and is discontinuous on surface of the second substrate.

19. A method for bonding semiconductor surfaces comprising:

providing a first substrate with a first bonding region with a first bonding surface, wherein the first bonding surface comprises a porosified surface which is formed in the first substrate and is part of first substrate material;

providing a second substrate with a second bonding region having a second conductive contact, wherein the second conductive contact comprises a TSV contact;

aligning the first bonding region with the second bonding region; and

bonding the second conductive contact directly to the porosified surface of the first bonding region by applying pressure at an elevated temperature.

20. The method of claim 19 comprises forming the porosified surface in the first bonding region, wherein forming the porosified surface comprises stain etching or anodization.

21. The method of claim 19 wherein bonding comprises eutectic bonding or thermo-compression bonding.

22. The method of claim 21 wherein:

the first substrate comprises a MEMS device; and

the second substrate comprises a CMOS device.

23. The method of claim 19 wherein the porosified surface comprises silicon, germanium or silicon germanium.

24. A method of fabricating a MEMS structure comprising:

providing a first substrate comprising a MEMs device with a first bonding region with a first bonding surface, wherein the first bonding surface comprises a porosified surface;

providing a second substrate comprising a CMOS device with a second bonding region having a second conductive contact, wherein the second conductive contact comprises a TSV contact;

aligning the first bonding region with the second bonding region; and

bonding the second conductive contact directly to the porosified surface of the first bonding region by applying pressure at an elevated temperature.

25. The method of claim 24 wherein the porosified surface comprises silicon, germanium or silicon germanium.

26. The method of claim 25 wherein bonding comprises eutectic bonding or thermo-compression bonding.