Erasable programmable single-ploy nonvolatile memory

• US 8,941,167 B2
• Filed: 03/08/2012
• Issued: 01/27/2015
• Est. Priority Date: 03/08/2012
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Wei-Ren, Hsu, Te-Hsun, Wang, Shih-Chen, Chen, Hsin-Ming, Yang, Ching-Sung
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/415,185
• Publication Number:
  US 20130234227A1
• Time in Patent Office: 1,055 Days
• Field of Search: 257/314, 257/315, 257/316, 257/320, 257/318
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

Claims

1. An erasable programmable single-poly nonvolatile memory, comprising:

a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage;

a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and

an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to an erase line voltage and a P-type region connected to a P-well voltage, and the n-type doped region is constructed in the P-type region;

wherein a first portion of the floating gate over the first N-well region is a p-type gate and a second portion of the floating gate over the erase gate region is a n-type gate.

2. An erasable programmable single-poly nonvolatile memory, comprising:

a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage;

a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and

an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to a second N-well voltage, a fourth p-type doped region connected to an erase line voltage and a second N-well region, and the n-type doped region and the fourth p-type doped region are constructed in the second N-well region.

3. The erasable programmable single-poly nonvolatile memory as claimed in claim 2, wherein the floating gate over the first N-well region and the second N-well region is a p-type gate.

4. The erasable programmable single-poly nonvolatile memory as claimed in claim 2, wherein the first N-well region and the second N-well region are completely isolated from each other by arranging an isolation structure and a P-type region between the first N-well region and the second N-well region and the P-type region is connected to a P-well voltage.

5. The erasable programmable single-poly nonvolatile memory as claimed in claim 4, wherein in a programmed state, a first voltage is provided as the source line voltage and the first N-well voltage, so that a plurality of hot carriers are injected into the floating gate.

6. The erasable programmable single-poly nonvolatile memory as claimed in claim 5, wherein in the programmed state, a ground voltage is provided as the bit line voltage, the P-well voltage, the erase line voltage and the second N-well voltage.

7. The erasable programmable single-poly nonvolatile memory as claimed in claim 4, wherein in an erased state, a second voltage is provided as the erase line voltage and the second N-well voltage, so that a plurality of stored carriers are removed from the floating gate and discharged out of the nonvolatile memory through the erase gate region.

8. The erasable programmable single-poly nonvolatile memory as claimed in claim 7, wherein in the erased state, a ground voltage is provided as the bit line voltage, the P-well voltage, the first N-well voltage and the source line voltage.

9. The erasable programmable single-poly nonvolatile memory as claimed in claim 2, further comprising an assist gate region adjacent to the floating gate, wherein the assist gate region comprises a second n-type doped region connected to an assist gate voltage, a n-lightly doped drain region under the floating gate, and a P-well region connected to a P-well voltage, wherein the second n-type doped region and the n-lightly doped drain region are constructed in the P-well region.

10. The erasable programmable single-poly nonvolatile memory as claimed in claim 9, wherein the P-well region is arranged between the first N-well region and the second N-well region, and the first N-well region and the second N-well region are completely isolated from each other.

11. The erasable programmable single-poly nonvolatile memory as claimed in claim 9, wherein in a programmed state, a first voltage is provided as the source line voltage and the first N-well voltage, and a third voltage is provided as the assist gate voltage, so that a plurality of hot carriers are injected into the floating gate.

12. The erasable programmable single-poly nonvolatile memory as claimed in claim 11, wherein the third voltage is provided as the assist gate voltage after the first voltage has been provided as the source line voltage and the first N-well voltage for a delay time.

13. The erasable programmable single-poly nonvolatile memory as claimed in claim 12, wherein in the programmed state, a ground voltage is provided as the bit line voltage, the P-well voltage, the erase line voltage and the second N-well voltage.

14. An erasable programmable single-poly nonvolatile memory, comprising:

a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage;

a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and

an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to an erase line voltage, double diffused drain region, and a P-well region connected to a P-well voltage, and the n-type doped region is constructed in the double diffused drain region and the double diffused drain region is constructed in the P-well region.

15. The erasable programmable single-poly nonvolatile memory as claimed in claim 14, wherein a thickness of a gate oxide above the erase gate region is smaller than a thickness of gate oxide under the floating gate.

16. The erasable programmable single-poly nonvolatile memory as claimed in claim 14, wherein an isolation structure is arranged between the P-well region and the N-well region.

17. The erasable programmable single-poly nonvolatile memory as claimed in claim 14, wherein in a programmed state, a first voltage is provided as the source line voltage and the first N-well voltage, so that a plurality of hot carriers are injected into the floating gate.

18. The erasable programmable single-poly nonvolatile memory as claimed in claim 17, wherein in the programmed state, a ground voltage is provided as the bit line voltage, the P-well voltage and the erase line voltage.

19. The erasable programmable single-poly nonvolatile memory as claimed in claim 14, wherein in an erased state, a second voltage is provided as the erase line voltage, so that a plurality of stored carriers are removed from the floating gate and discharged out of the nonvolatile memory through the erase gate region.

20. The erasable programmable single-poly nonvolatile memory as claimed in claim 19, wherein in the erased state, a ground voltage is provided as the bit line voltage, the P-well voltage, the N-well voltage and the source line voltage.