Erasable programmable single-ploy nonvolatile memory
First Claim
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1. An erasable programmable single-poly nonvolatile memory, comprising:
- a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage;
a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and
an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to an erase line voltage and a P-type region connected to a P-well voltage, and the n-type doped region is constructed in the P-type region;
wherein a first portion of the floating gate over the first N-well region is a p-type gate and a second portion of the floating gate over the erase gate region is a n-type gate.
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Abstract
An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
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Citations
20 Claims
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1. An erasable programmable single-poly nonvolatile memory, comprising:
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a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to an erase line voltage and a P-type region connected to a P-well voltage, and the n-type doped region is constructed in the P-type region; wherein a first portion of the floating gate over the first N-well region is a p-type gate and a second portion of the floating gate over the erase gate region is a n-type gate.
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2. An erasable programmable single-poly nonvolatile memory, comprising:
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a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to a second N-well voltage, a fourth p-type doped region connected to an erase line voltage and a second N-well region, and the n-type doped region and the fourth p-type doped region are constructed in the second N-well region. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An erasable programmable single-poly nonvolatile memory, comprising:
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a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the first PMOS transistor is constructed in a first N-well region connected to a first N-well voltage, the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the second PMOS transistor is constructed in the first N-well region, the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type doped region connected to an erase line voltage, double diffused drain region, and a P-well region connected to a P-well voltage, and the n-type doped region is constructed in the double diffused drain region and the double diffused drain region is constructed in the P-well region. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification