Ultra low power analog to digital interface using range adaptive techniques

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First Claim
1. A method, comprising:
 receiving an analog signal by an analogtodigital (A/D) converter having a full scale range and a total number of bits spanning the full scale range; and
converting the analog signal to a digital signal by the A/D converter over a plurality of conversion cycles using an adaptable number of comparisons made between a sample of the analog signal and a test signal on at least a current conversion cycle of the plurality of conversion cycles, wherein the adaptable number of comparisons comprises a number of comparisons less than the number of comparisons required to convert the analog signal over the full scale range.
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Abstract
A medical device and associated method convert an analog signal using an adaptable number of comparisons between the analog signal and a reference signal. The medical device includes an analogtodigital (A/D) converter for receiving an analog signal. The A/D converter has a full scale range and a total number of bits spanning the full scale range. The A/D converter converts the analog signal to a digital signal over conversion cycles using an adaptable number of comparisons. For at least one of the conversion cycles, the adaptable number of comparisons is less than the total number of comparisons required to convert the analog signal over the full scale range of the A/D converter.
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22 Claims
 1. A method, comprising:
 receiving an analog signal by an analogtodigital (A/D) converter having a full scale range and a total number of bits spanning the full scale range; and
converting the analog signal to a digital signal by the A/D converter over a plurality of conversion cycles using an adaptable number of comparisons made between a sample of the analog signal and a test signal on at least a current conversion cycle of the plurality of conversion cycles, wherein the adaptable number of comparisons comprises a number of comparisons less than the number of comparisons required to convert the analog signal over the full scale range.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
 receiving an analog signal by an analogtodigital (A/D) converter having a full scale range and a total number of bits spanning the full scale range; and
 12. A medical device, comprising an analogtodigital (A/D) converter configured to receive an analog signal and having a full scale range and a total number of bits spanning the full scale range, the A/D converter configured to convert the analog signal to a digital signal over a plurality of conversion cycles using an adaptable number of comparisons on at least a current conversion cycle of the plurality of conversion cycles, the adaptable number of comparisons comprising a number of comparisons less than a number of comparisons required to convert the analog signal over the full scale range.
 21. A medical device, comprising:
 receiving means for receiving an analog signal;
converting means for converting the analog signal to a digital signal over a plurality of conversion cycles, the converting means having a full scale range; and
controlling means for adjusting an adaptable number of comparisons performed by the converting means for converting the analog signal over the plurality of conversion cycles, the adaptable number of comparisons being less than the number of comparisons required to convert the analog signal over the full scale range.
 receiving means for receiving an analog signal;
 22. A nontransitory computer readable storage medium storing a set of instructions executable by a control module of an analogtodigital (A/D) converter having a full scale range and a total number of bits spanning the full scale range included in a medical device, the instructions causing the A/D converter to:
 convert the analog signal to a digital signal over a plurality of conversion cycles using an adaptable number of comparisons made between a sample of the analog signal and a test signal on at least a current conversion cycle of the plurality of conversion cycles, wherein the adaptable number of comparisons comprises a number of comparisons less than the number of comparisons required to convert the analog signal over the full scale range.
1 Specification
The disclosure relates to medical devices capable of converting analog signals to digital signals using an adaptive number of bits.
Numerous implantable medical devices (IMDs) are available for acute or chronic implantation within patients. Some implantable medical devices may be used to monitor physiological signals of the patient, such as cardiac pacemakers, implantable hemodynamic monitors, implantable cardiac monitors (sometimes referred to as implantable loop recorders or ECG monitors), implantable blood chemistry monitors, implantable pressure monitors, etc. Among the various types of physiological sensors utilized by medical devices for monitoring patients are electrodes for measuring electrical signals and/or impedances, piezoelectric crystals, accelerometers, pressure sensors, pH sensors, acoustical sensors, temperature sensors, and oxygen sensors.
The physiological signals may be stored, processed and analyzed by the medical device to generate physiological data about a patient useful to a clinician in diagnosing a condition or planning medical treatment. Some implantable devices may be configured to deliver a therapy in conjunction with monitoring of physiological signals. Physiological signals may be processed and analyzed to determine when a therapy is needed or how a therapy needs to be adjusted to benefit the patient. Therapies delivered by an implantable medical device can include electrical stimulation therapies, e.g., cardiac pacing, cardioversion/defibrillation shock pulses, or neurostimulation, and pharmacological or biological fluid delivery therapies.
In order to provide the physiological data needed for detecting pathological conditions, controlling automatic therapy delivery or generating data in a form useful to a clinician for diagnosis and prognosis, an analog signal produced by a physiological sensor often needs to be digitized. An analogtodigital (A/D) converter is used to convert the analog signal to a digital signal according to a desired sampling rate and bit resolution. When physiological signals are monitored continuously or on a frequent basis, A/D converters included in an IMD can contribute significantly to the overall device power consumption.
An ongoing design goal in medical device technology is device size reduction, e.g. to enable minimally invasive implant procedures and to promote patient comfort. Reduction of device size, however, poses limitations on the space available for power supplies, signal processing circuitry, and other device components that support the primary device function. Systems and methods that reduce the power consumption required by signal processing circuitry, such as A/D converters, can improve the battery longevity of implantable devices and/or contribute to an overall size reduction.
In general, the disclosure is directed towards techniques for converting analog signals to digital signals in medical devices. A selfadjusting A/D converter automatically adjusts the number of comparisons made between an analog input signal and a reference signal during a conversion cycle.
In one example, a selfadjusting A/D converter including a digital converter and a conversion control module converts an analog input signal to a digital signal using an adaptable number of bits. One method for converting an analog signal to a digital signal includes receiving an analog signal by an A/D converter. The A/D converter has a full scale range and a total number of bits spanning the full scale range. The method further includes converting the analog signal to a digital signal over conversion cycles using an adaptable bit number so that on at least a portion of the conversion cycles an adapted number of bits less than the total number of bits spanning the full scale range is used by the A/D converter to convert the analog signal. The adapted number of bits spans a portion of the full scale range that is less than the full scale range of the total number of available bits.
In another embodiment, a medical device includes an analogtodigital (A/D) converter configured to receive an analog signal. The A/D converter has a full scale range and a total number of bits spanning the full scale range. The A/D converter includes a digital converter configured to convert the analog signal to a digital signal over conversion cycles using an adaptable bit number. On at least a portion of the conversion cycles, an adapted number of bits that spans a portion of the full scale range less than the total number of bits is used to convert the analog signal.
In another example, a medical device includes receiving means for receiving an analog signal, converting means for converting the analog signal to a digital signal over conversion cycles, and controlling means for adjusting an adaptable number of bits used by the converting means for converting the analog signal over the conversion cycles. The adaptable number of bits spans less than a full scale range of the converting means for at least one of the conversion cycles.
In other examples, a computer readable storage medium stores a set of instructions executable by a control module of an analogtodigital (A/D) converter included in a medical device. The instructions cause the control module to enable the A/D converter to convert an analog signal to a digital signal over conversion cycles using an adaptable bit number. The instructions further cause the control module to adjust the adaptable bit number so that on at least a portion of the conversion cycles an adapted number of bits is used to convert the analog signal. The adapted number of bits spans a portion of a full scale range of the A/D converter less than the full scale range spanned by the total number of available bits of the A/D converter.
In another example, a medical device has an analogtodigital (A/D) converter configured to receive an analog signal and having a full scale range and a total number of bits spanning the full scale range. The A/D converter is configured to convert the analog signal to a digital signal over conversion cycles using an adaptable number of comparisons on a portion of the conversion cycles, wherein the adaptable number of comparisons is a number of comparisons that is less than the number of comparisons required to convert the analog signal over the full scale range.
The details of one or more aspects of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.
Examples of implantable medical devices in which the signal processing techniques disclosed herein may be implemented include cardiac pacemakers, implantable cardioverter defibrillators (ICDs), cardiac monitors such as hemodynamic monitors or ECG recorders, neurostimulators configured for delivering electrical stimulation to and monitoring activity of peripheral nerves and/or portions of the central nervous system, electroencephalogram (EEG) monitors, electromyogram (EMG) monitors, drug pumps or other fluid delivery devices, oxygen monitors, flow monitors, pressure monitors, impedance monitors, acoustical monitors, activity monitors, motion monitors, or any other implantable device configured for sensing a physiological signal. The apparatus and techniques disclosed herein may alternatively be implemented in an external device which may be a wearable patient monitor or a bedside patient monitor. The system100shown in
System100includes IMD10coupled to leads118, 120, and122which carry multiple electrodes. IMD10is configured for bidirectional communication with programmer170. IMD10may be, for example, an implantable pacemaker or implantable cardioverter defibrillator (ICD) that provides electrical signals to heart112via electrodes coupled to one or more of leads118, 120, and122for pacing, cardioverting and defibrillating the heart112. IMD10is capable of delivering pacing in one or more heart chambers, and in the embodiment shown, is configured for multichamber pacing and sensing in the right atrium (RA) 126, the right ventricle (RV) 128, and the left ventricle (LV) 132using leads118, 120and122.
IMD10delivers RV pacing pulses and senses RV intracardiac electrogram (EGM) signals using RV tip electrode140and RV ring electrode142. RV lead118is shown to carry a coil electrode162which may be used for delivering high voltage cardioversion or defibrillation shock pulses. IMD10senses LV EGM signals and delivers LV pacing pulses using the electrodes144carried by a multipolar coronary sinus lead120, extending through the RA126and into a cardiac vein130via the coronary sinus. In some embodiments, coronary sinus lead120may include electrodes positioned along the left atrium (LA) 136for sensing left atrial (LA) EGM signals and delivering LA pacing pulses. RV lead118is further shown to carry a sensor190, which may be a pressure sensor, accelerometer, oxygen sensor, or other type of physiological sensor generating an analog signal that may be converted to a digital signal for analysis by IMD10.
IMD10senses RA EGM signals and delivers RA pacing pulses using RA lead122, carrying tip electrode148and ring electrode150. RA lead122is shown to be carrying coil electrode166which may be positioned along the superior vena cava (SVC) for use in delivering cardioversion/defibrillation shocks. In other embodiments, RV lead118carries both the RV coil electrode162and the SVC coil electrode166. IMD10may detect tachyarrhythmias of heart112, such as fibrillation of ventricles128and132, and deliver high voltage cardioversion or defibrillation therapy to heart112in the form of electrical shock pulses. Pacing and sensing of the cardiac chambers is typically achieved using the pace/sense electrodes140, 142, 144, 148and150, however in some embodiments coil electrodes162and/or166may be used in sensing and/or pacing electrode vectors.
While IMD10is shown in a right pectoral implant position in
IMD10includes internal circuitry for performing the functions attributed to IMD10. Housing160encloses the internal circuitry. It is recognized that the housing160or portions thereof may be configured as an active electrode158for use in cardioversion/defibrillation shock delivery or used as an indifferent electrode for unipolar pacing or sensing configurations with any electrodes carried by leads118, 120and122. IMD10includes a connector block134having connector bores for receiving proximal lead connectors of leads118, 120and122. Electrical connection of electrodes or other sensors carried by leads118, 120and122and IMD internal circuitry is achieved via various connectors and electrical feedthroughs included in connector block134.
While a multichamber ICD is shown in
Programmer170includes a display172, a processor174, a user interface176, and a communication module178including wireless telemetry circuitry for communication with IMD10. In some examples, programmer170may be a handheld device or a microprocessorbased home monitor or bedside programming device. A user, such as a physician, technician, nurse or other clinician, may interact with programmer170to communicate with IMD10. For example, the user may interact with programmer170via user interface176to retrieve currently programmed operating parameters, physiological data collected by IMD10, or devicerelated diagnostic information from IMD10. A user may also interact with programmer170to program IMD10, e.g., select values for operating parameters of the IMD.
Programmer170includes a communication module178to enable wireless communication with IMD10. Examples of communication techniques used by system100include low frequency or radiofrequency (RF) telemetry, which may be an RF link established via Bluetooth, WiFi, or MICS for example. In some examples, programmer170may include a programming head that is placed proximate to the patient's body near the IMD10implant site, and in other examples programmer170and IMD10may be configured to communicate using a distance telemetry algorithm and circuitry that does not require the use of a programming head and does not require user intervention to maintain a communication link.
The A/D conversion techniques disclosed herein may be implemented in programmer170for processing signals received from IMD10and/or for processing signals acquired directly by programmer170, e.g. ECG signals using external surface electrodes.
It is contemplated that programmer170may be coupled to a communications network via communications module178for transferring data to a remote database or computer to allow remote monitoring and management of patient114using the techniques described herein.
Modules80, 84, 86, 88, 92, memory82, sensors90, and accelerometer94shown in
The functions attributed to IMD10herein may be embodied as one or more processors, hardware, firmware, software, or any combination thereof. Depiction of different features as discrete modules or components is intended to highlight different functional aspects and does not necessarily imply that such modules must be realized by separate hardware or software components. Rather, functionality associated with one or more modules may be performed by separate hardware or software components, or integrated within common or separate hardware or software components. For example, sensing interface92for receiving and converting analog electrical signals received from other IMD modules or sensors may be implemented in hardware and software included in processor80and memory82.
In some examples, sensing interface92is configured to receive one or more analog signals from electrical sensing module86, sensors90, and/or accelerometer94. Sensing interface92includes an A/D converter for converting analog signals to digital signals. Processor80receives the converted digital signals and may analyze the digital signals for detecting a patient condition, controlling a therapy delivered by signal generator84, and/or storing patient data in memory82for later transmission via telemetry module88. As will be described in greater detail herein, the A/D converter included in sensing interface92uses an adaptive successive approximation register (ASAR) having an adjustable number of bits used to convert an analog signal to a digital signal in one embodiment. In other embodiments, other types of digital converters may be used, such as a flash converter using an adaptable number of comparators enabled to perform comparisons between an input analog signal and a reference signal.
A power source96provides power to each of the other modules and components of IMD10as required. Processor80may execute power control operations to control when various components or modules are powered to perform various IMD functions. Power source96may include one or more energy storage devices, such as one or more rechargeable or nonrechargeable batteries. Processor80may also be configured to perform diagnostic testing of IMD10, which may include monitoring the remaining charge of power source96and providing a replacement or recharge indicator, for example. The connections between power source96and processor80and other IMD modules and components are not shown for the sake of clarity.
In some examples, sensing interface92may receive internal IMD signals from power source96, signal generator84, processor80or other IMD modules or components for digitizing signals for use in device diagnostic testing, such as testing charging or output circuitry included in signal generator84, testing charge of power source96, validating or coding/decoding communication signals received or produced by telemetry88, or other device functions. Accordingly, sensing interface92may be configured to convert one or more analog signals, which may be physiological signals received from sensors90, accelerometer94, or electrical sensing module86and/or devicerelated signals produced by internal IMD circuits or modules such as power source96, telemetry module88or signal generator84.
Memory82may include computerreadable instructions that, when executed by processor80, cause IMD10and processor80to perform various functions attributed throughout this disclosure to IMD10, processor80, and sensing interface92. The computerreadable instructions may be encoded within memory82. Memory82may include any nontransitory, computerreadable storage media including any volatile, nonvolatile, magnetic, optical, or electrical media, such as a random access memory (RAM), readonly memory (ROM), nonvolatile RAM (NVRAM), electricallyerasable programmable ROM (EEPROM), flash memory, or other digital media with the sole exception being a transitory propagating signal.
Processor and control module80may include any one or more of a microprocessor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), or equivalent discrete or integrated logic circuitry. In some examples, processor80may include multiple components, such as any combination of one or more microprocessors, one or more controllers, one or more DSPs, one or more ASICs, or one or more FPGAs, as well as other discrete or integrated logic circuitry. The functions attributed to processor80herein may be embodied as software, firmware, hardware or any combination thereof. In one example, sensing interface92may, at least in part, be stored or encoded as instructions in memory82that are executed by processor and control module80.
Processor and control module80includes a therapy control module that controls signal generator84to deliver electrical stimulation therapy, e.g., cardiac pacing, to heart112according to a selected one or more therapy programs, which may be stored in memory82. Signal generator84is electrically coupled to electrodes140, 142, 144A144D (collectively144), 148, 150, 158, 162, and166 (all of which are shown in
Signal generator84may include a switch module (not shown) and processor and control module80may use the switch module to select, e.g., via a data/address bus, which of the available electrodes are used to deliver pacing pulses. Processor80controls which of electrodes140, 142, 144A144D, 148, 150, 158, 162, and166is coupled to signal generator84for delivering stimulus pulses, e.g., via the switch module. The switch module may include a switch array, switch matrix, multiplexer, or any other type of switching device suitable to selectively couple a signal to selected electrodes.
Electrical sensing module86monitors cardiac electrical signals for sensing cardiac electrical events, e.g. Pwaves and Rwaves, from selected ones of electrodes140, 142, 144A144D, 148, 150, 158, 162, or166in order to monitor electrical activity of heart112. Sensing module86may also include a switch module to select which of the available electrodes are used to sense the cardiac electrical activity. In some examples, processor80selects the electrodes to function as sense electrodes, or the sensing vector, via the switch module within sensing module86.
Sensing module86may include multiple sensing channels, each of which may be selectively coupled to respective combinations of electrodes140, 142, 144A144D, 148, 150, 158, 162, or166to detect electrical activity of a particular chamber of heart112. Each sensing channel may comprise an amplifier that outputs an indication to processor80in response to sensing of a cardiac depolarization, in the respective chamber of heart112. In this manner, processor80may receive sense event signals corresponding to the occurrence of Rwaves and Pwaves in the various chambers of heart112, e.g. ventricular sense events and atrial sense events corresponding to intrinsic depolarization of the respective heart chamber.
Sensing module86may further provide analog signals received via electrodes140, 142, 144A144D, 148, 150, 158, 162, and166to sensing interface92for conversion to digital signals. For example, digitized EMG signals may be analyzed by processor80for detecting and discriminating cardiac arrhythmias, detecting Twave alternans, detecting cardiac ischemia or other cardiac conditions. Accordingly, sensing interface92may include multiple A/D converters corresponding to each of the sensing channels included in sensing module86. Other electrical signals that may be received from electrical sensing module86may include electrical impedance signals that may be used to monitor lead impedance, cardiac impedance, thoracic impedance or other impedance values of interest.
Accelerometer94may be embodied as a onedimensional, twodimensional, or threedimensional accelerometer including one or more DC or AC accelerometers or other motion sensitive devices. Examples of accelerometers used for sensing patient activity and/or posture are generally described in U.S. Pat. No. 5,593,431 (Sheldon), and U.S. Pat. No. 6,044,297 (Sheldon), both of which are hereby incorporated herein by reference in their entirety. An accelerometer signal used for monitoring patient activity may be analyzed for providing an activityindicated heart rate for controlling cardiac pacing or for other patient monitoring, therapy control or diagnostic purposes.
In one example, an A/D converter included in sensing interface92for receiving an accelerometer signal may have a full scale range of +2 G to encompass earth gravity (1G) plus a 1G range that covers typical human activities. The full scale range of 4G, (−2G to +2G) accommodates instances when the orientation of the accelerometer changes resulting in a signal polarity change. A majority of time a patient will be at relatively low levels of activity, e.g. resting or normal activities of daily living, such that the accelerometer signal will vary within only a portion of the full scale range of the A/D converter. Less often, the accelerometer signal amplitude may extend close to the full range of the A/D converter for brief periods time, e.g. during bouts of high levels of physical activity or exertion. Generally, the accelerometer signal will vary within a smaller range than the full scale range of the A/D converter during any given activity level. The variation will remain within a smaller range than the full scale range for a vast majority of the time for most patients.
Digital conversions utilizing the full scale range of the A/D converter for every sample point of an accelerometer signal are, therefore, consuming power to convert bits that may not need to be utilized on every conversion cycle. An A/D converter as disclosed herein utilizes an adaptable number of bits set on each conversion cycle to conserve power consumption by the A/D converter. An A/D converter having an adaptable number of bits and associated conversion techniques as disclosed herein are appropriate for use with an analog signal that requires a relatively large full scale range but typically remains within only a portion of that range for extended periods of time.
As described herein, the sensing interface92may include one or more A/D converters each having an ASAR for converting a received signal using an adaptable bit number. The adaptable bit number may be reduced from the full scale bit number to reduce the time required to convert an analog signal sample to a digital signal. An A/D conversion cycle is the time required to convert an analog signal sample point to an Nbit digital word. A/D conversion by a successive approximation register (SAR) is normally performed bitbybit to set each bit to a digital high or digital low value for all N bits. A conversion cycle is not completed until all available bits in the Nbit digital word have been set. The duration of a conversion cycle can be referred to as the “bit time” and is normally equal to the total number of available bits used to cover the full scale range of an A/D converter having an SAR. For example, if an 8bit A/D converter is used, a single conversion cycle will require a bit time of 8. An ASAR as disclosed herein enables an overall reduction in the average conversion cycle bit time by using an adaptable number of bits which is less than the total number of available bits for at least some conversion cycles. A reduction in overall average bit time conserves the IMD power supply. Other types of A/D converters may be configured to adapt a number of bits or a number of comparisons used per conversion cycle using the techniques disclosed herein.
A patient activity or posture signal that does not vary rapidly relative to a sampling rate and that remains within a smaller range than the full scale A/D converter range for extended periods of time is one illustrative example of a signal that may be converted using the methods described herein to significantly reduce the overall average bit time. Numerous other physiological and/or internal IMD signals may be converted using the methods disclosed herein to conserve power by reducing the average conversion cycle time. Sensing interface92may therefore receive signals from any of accelerometer94, sensors90, electrical sensing module86, or any internal IMD components or modules and may include a required number of A/D converters having ASARs or other adaptable digital converters for converting the received analog signals using an adaptable number of comparisons per conversion cycle.
Vin201is received by ASAR202. ASAR202includes a track and hold circuit214to sample the analog input signal Vin201at a desired sampling rate and hold the value of an analog signal sample Ai215during a conversion cycle. The illustrative embodiments described herein pertain to a voltage converter. The conversion techniques disclosed herein however, may be utilize an adaptive number of bits for any conversion that uses successive approximations to generate a digitized sequence of results. For example, the techniques disclosed herein may be utilized in converters configured to convert current, resistance, capacitance, light intensity, or other received signals.
During the conversion cycle, ASAR202performs a search algorithm to converge upon a digital estimation of Ai215. In one example, ASAR202performs a bitbybit binary search to determine a digital word representation of the analog signal sample Ai215. The binary search includes comparing Ai215to an approximated voltage signal Vdac205. Vdac205is an analog voltage test signal produced by digitaltoanalog (DAC) converter210included in ASAR202. DAC210receives a digital “guess” or approximation of Mi, the digitized value of Ai215, from adaptable bit register208. The digital approximation Mi is converted to an analog signal Vdac205for providing a test signal that is compared to Ai215by comparator212during the binary search algorithm. DAC210converts the digital approximation Mi to Vdac205using an input reference signal Vref204. Vref204may be an input voltage signal provided by power supply96. Vref204may be equal to the full range of A/D converter200when A/D converter200has a range from 0V to +Vref or may be equal to half the full scale range when A/D converter200has a range from −Vref to +Vref.
In past A/D converters that utilize a successive approximation register (SAR), the SAR converts an analog input signal to a digital word using successive approximations of an analog signal sample in a search algorithm. Typically, an A/D converter using a SAR will perform a binary search by initially approximating the analog signal sample to be equal to the midway point of the fullscale range of the A/D converter, e.g. Vref/2 for a range from 0 to Vref or a midway point of 0 V when the full scale range is −Vref to +Vref. This midway point would correspond to a most significant bit set to digital high (e.g. 1) with all lower bits set to digital low (e.g. 0). If the analog signal is greater than the midway point, the most significant bit remains set at digital high and the next most significant bit is set to digital high for the next approximation. This next approximation is converted to an analog voltage signal by the internal DAC and compared to the analog signal sample. If the analog signal sample is still greater than the next approximation, the next most significant bit remains set at digital high. If the analog signal sample is less than the next approximation, the next most significant bit is set at digital low. After setting the next most significant bit based on the comparator output, the comparison process continues bitbybit until all bits have been set and a digital output is produced. The digital output is the converged upon digital value of the input voltage.
The next analog signal sample point will not be digitized until the conversion cycle for the current analog signal sample is complete. The bitbybit binary search process repeats for the next input signal sample during the next conversion cycle by resetting the initial approximation of the analog signal to the fullrange midway point. Each conversion cycle uses all bits covering the full range of the A/D converter. Each conversion cycle, therefore, is started with an initial approximation equal to the midway point of the A/D converter full scale range and requires a bit time equal to N where N is the total number of bits spanning the full scale range.
In contrast, the selfadjusting A/D converter202disclosed herein uses an adaptable initial approximation of Mi and/or an adaptable bit number for converting Ai to the digital value Mi. ASAR202receives as input a bit control parameter, referred to herein as “BIT CONTROL” 224and an initial digital approximation Minitial222of Ai from conversion control module220. Methods performed by ASAR202and conversion control module220for adjusting BIT CONTROL224, adjusting the adaptable bit number used for each conversion cycle, and setting the initial approximation Minitial222will be described below in conjunction with
ASAR logic206sets the number of bits used out by adaptable bit register208for each conversion cycle according to BIT CONTROL224received from conversion control module220. BIT CONTROL224is an adjustable number set by conversion control module220and used by ASAR logic206to set the adapted bit number equal to or less than the total number of available bits corresponding to the full scale range of A/D converter200. For example, if A/D converter200has an 8 bit resolution over a full range of ±Vref, the adapted bit number may be 8 bits or less. A fewer number of bits than the total number of available bits are used for at least some conversion cycles to shorten the overall average conversion cycle time and reduce power consumed by A/D converter200.
ASAR logic206provides the initial approximation Minitial222to adaptable bit register208. Minitial222is set equal to the most recent previous digital output Mout230in some examples. Alternatively, Minitial222may be set as a function of one or more most recent digital outputs. In this way Mi, the digitized value of Ai generated by ASAR202, is initially approximated based on the digital value(s) of a predetermined number of most recent digitized output values Mout230of Vin201. When Minitial222is set equal to Mout230from the most recent previous conversion cycle, it is assumed that Vin201does not vary rapidly relative to the sampling rate of track and hold circuit214.
Without changing the bit resolution of A/D converter200, the number of bits used by adaptable bit register208for generating Mi216is set by ASAR logic206. An adapted bit number that is less than the total number of available bits has a range that is a portion of the full scale range of A/D converter200that is less than the full scale range. The bit resolution is the same regardless of the number of bits used. The range of the adapted bit number may be centered on the initial approximation of Mi in some examples. In other words, the adapted bit number may have a range that is not centered on the midway point of the full scale range.
The initial digital approximation Minitial222is converted to an analog signal by DAC210to produce Vdac205as input to comparator212. Vdac205is compared to Ai215by comparator212. The output of comparator212is provided as feedback to ASAR logic206, which responds by controlling adaptable bit register208to set the current bit to digital high if Ai215is greater than Vdac or digital low if Ai215is less than Vdac205. ASAR logic206increments or decrements the next approximation of Ai based on the current bit value. For example, if the adaptable bit number has been adjusted to 4 bits, the next approximation of Ai215will be incremented or decremented from Minitial by 8 digital units, half of the 16 digital units of the most significant bit of the four bits.
The digital word representing the next approximation of Ai215is provided to DAC210, converted to an analog signal Vdac205, and compared to Ai215by comparator212. The result of the comparison is used to adjust the next approximation up or down by half the current bit resolution. This process continues until all bits of the adjusted number of bits have been set.
Examples of successive approximations of Ai215during a binary search for Mi216, the digital value of Ai215generated by ASAR202, are shown and described in conjunction with
ASAR logic206may count the number of times the approximation of Ai is successively decremented or successively incremented during the binary search. This count is referred to here as the “successive adjustment count” and is an indication of whether Ai215is within the range of the adapted bit number being used for the conversion cycle. As will be further described below, this successive adjustment count, provided as the output COUNT218by SAR202, is used by conversion control module220to determine BIT CONTROL224, used for setting the adjusted number of bits during the next conversion cycle. For example, if COUNT indicates Ai215is outside the range of the adapted bit number, the bit number will be increased on the next conversion cycle.
COUNT218indicates whether Ai215is likely within the range of the adapted bit number used for the ith conversion cycle and represents one method for making this determination. To illustrate, if COUNT218is equal to the adjusted number of bits, this count indicates that every successive approximation of Ai215during the binary search was adjusted in the same direction, either always increased or always decreased. For example, the approximation of Ai was repeatedly and sequentially increased in response to every bit comparison of Vdac205to Ai215or it was sequentially and repeatedly decreased in response to every bit comparison. Ai was either always greater than every successive approximation or always less than every successive approximation during the bitbybit search for Mi. This indicates Ai215is likely outside the range of the adapted bit number, i.e. either greater than or less than the range of the adapted bit number.
If the COUNT218indicates Ai215is likely to be out of the range of the adapted bit number, the conversion control module220determines that the conversion cycle is not complete. Conversion control module220may set BIT CONTROL224to the maximum number of bits available, and a full bit conversion is performed over the full scale range of A/D converter200by ASAR202. The full bit conversion may be performed starting with the same initial approximation Minitial as the previously attempted conversion cycle. Alternatively, the full bit conversion may be performed starting with an initial approximation Minitial222equal to a midway point of the full A/D converter range. The output Mi216of the full bit conversion is then provided by A/D converter200as the digital output value Mout230of Ai215.
If COUNT218is less than the adapted bit number at the end of a given conversion cycle, Ai215is likely within the adapted bit range because the convergence involved at least one successive approximation of Ai215being adjusted in an opposite direction as a previous approximation of Ai215. For example, an approximation of Ai215set by SAR logic206may have been increased in response to one bit comparison and decreased in response to a subsequent bit comparison. A sequence of successive approximations of Ai215that includes at least one change in direction indicates the binary search converged upon Ai within the adapted bit number range. The value of Mi216at the end of the conversion cycle is then deemed a valid digital representation of Ai215. The ith conversion cycle is determined to be complete by conversion control module220. The final approximation M_{i}216converged upon by ASAR202during the binary search using the adapted bit number is provided as the digital output signal Mout230for the ith signal sample Ai215by conversion control module220.
The embodiments described herein utilize an ASAR performing successive approximations during a binary search for Mi216. In other embodiments, other nonbinary search algorithms could be used. For example, the successive approximation could determine two bits at a time, in order to speed the processing. This would require multiple comparators to operate at each comparison point, and multiple quantized levels of voltage (or current, charge, etc.) to be generated for comparison purposes. Furthermore, it is contemplated that aspects of the techniques disclosed herein could be implemented using other types of A/D converters besides converters that use a successive approximation register.
The starting point302of conversion cycle301is the initial approximation Minitial of Ai305. Minitial302is equal to the midway point (0 V in this example) of the full scale range, −Vref to +Vref. This initial approximation302is set by setting the most significant bit (MSB) 7to digital high (e.g., 1) and setting all other bits to digital low (e.g., 0). Upon comparing the initial approximation302to Ai305, the ASAR logic sets the MSB to digital low because Ai305is less than the initial approximation302. ASAR logic decreases the next approximation304of Ai305by setting the next most significant bit to digital high. Since approximation304is less than Ai305, the ASAR logic will increment the next approximation306, and so on. This binary search process continues bitbybit for all eight bits.
A portion of conversion cycles301and307is shown with an enlarged vertical scale in the ellipse330. The enlarged scale enables the convergence of the successive approximations following each bit comparison to be more easily viewed.
As shown in
An adapted bit number conversion cycle307starts at point308. In this example, the bit number has been automatically adjusted to 4 based on previous conversion cycles as will be described in conjunction with
The initial approximation Minitial represented by point308in the adaptive conversion cycle307is set to the previous digitized value of Ai1 determined on the most recent, previous conversion cycle. In some cases, the analog input signal is not expected to change rapidly relative to the sampling rate. Accordingly, setting the initial approximation Minitial at the most recent previous digital output value Mout and using a reduced number of bits reduces the range over which the binary search is performed and starts the binary search at a reasonable predicted value of Mout. This narrowed binary search can reduce the conversion time required to converge on the digital value of Ai305since fewer bits are being used.
Each bit0through bit3is set by ASAR logic as needed to set Minitial308, which is converted to an analog signal Vdac by the DAC for comparison to Ai305. Upon the first comparison during the binary search, Minitial308is less than Ai305. ASAR logic will increment the next approximation310. The next approximation310is decremented by half the current bit value. For example, for bit3, the next digital approximation of Ai305will be decreased by 4 digital units (half of 8). Since Ai305is less than the next approximation310, the ASAR logic decreases the next successive approximation312by half the current bit value. The final approximation is the converged upon digital value Mi320of Ai305. The final values of Mi320for the full bit conversion cycle301and the adapted bit number conversion cycle307also converge, typically to the same digital value though there may be instances wherein the final converged value of the full bit conversion cycle301and the adapted bit conversion cycle307may be different.
The adapted bit number conversion cycle307has a bit time duration of four, significantly shorter than the fullrange 8bit conversion cycle duration322. Thus, by using an adapted bit number, a digital value Mi320of Ai305can be generated consuming less time and power.
After performing this first conversion cycle, the initial approximation Minitial for the next conversion cycle is set at block356. The initial approximation Minitial is set based on the digital output value Mout of at least one previous conversion cycle. Instead of starting each conversion cycle at the midpoint of the full scale range of the A/D converter, a starting prediction of Mi is made based on one or more recent Mout values. In one example, Minitial is set equal to Mout from the most recent previous conversion cycle (the ith1 cycle). In other examples, Minitial may be set equal to a mean, median, mode, xth largest absolute value out of y recent values, or another value based on a combination of a predetermined number of previous Mout values.
At block358, the selfadjusting A/D converter sets the adaptable bit number for the next conversion cycle. The adaptable bit number may be based on whether or not the previous converged value of Mi output by SAR logic was within a range of the bit number used on the previous conversion cycle, as will be described below and in conjunction with
At block360, the next (ith) conversion is performed by performing a binary search beginning at Minitial set for the current conversion cycle and using the number of bits set at block358. After converging on Mi, the SAR logic determines whether the value of Ai is likely within range of the number of bits used for the current conversion cycle. If the bit number has been reduced from the total number of available bits at block358, the adapted bit number has a range that is a portion less than the full scale range of the A/D converter, with each of the bits in the adjusted number of bits having the same bit resolution as the bit resolution assigned to each bit in the full scale range. In some instances, an input signal sample Ai may fall outside the adapted bit number range but within the full scale range of the A/D converter. If this happens, the bit number needs to be increased to obtain a correct value of Mi for Ai. However, as long as Ai remains in the range of the adapted bit number, A/D conversion can continue using a reduced number of bits thereby reducing the overall average conversion cycle time and A/D converter power consumption.
In one embodiment, determining whether Ai is within the current bit number range is made by the conversion control module by determining if all adjustments to the approximation of Mi were made in the same direction. For example, if all successive approximations of Mi during a binary search were increased from the previous approximation, Ai is likely greater than an upper boundary of the adapted bit number range. Likewise, if all successive approximations of Mi were decreased from the previous approximation, Ai is likely less than a lower boundary of the adapted bit number range.
Other methods for determining whether Ai is likely out of the current bit number range may be used. For example Mi may be compared to the boundaries of the current bit number range. If Mi is equal to a boundary value, Ai is deemed likely to be out of range.
If Ai is determined to likely be out of an adapted bit number range at block362, a control parameter used by the conversion control module for controlling the adaptable bit number on each conversion cycle is increased at block364. If Ai is out of the bit number range, the adaptable bit number is increased on the next conversion cycle in an attempt to capture Ai within the adapted bit number range.
In some embodiments, prior to advancing to the next conversion cycle to digitize A_{i+1}using the increased, adapted bit number, the ith conversion cycle will be repeated by returning to block354. Since Ai was determined to be out of the adapted bit number range, the value of Mi at the end of the ith conversion cycle may not be the correct digital value of Ai. The ith conversion cycle may be repeated using a broader range, i.e. a larger bit number, to obtain a correct value of Mi for the current signal sample Ai. A full bit conversion may be performed at block354to obtain a valid value Mi, within the full scale A/D converter range. Alternatively, the adaptable bit number may be increased by one or another predetermined increment for repeating the ith conversion cycle with a larger bit number spanning a larger portion of the full scale range of the A/D converter. After repeating the ith conversion cycle using an increased number of bits at block354, the digital output signal Mout is generated at block355, equal to the valid Mi value resulting from the repeated conversion cycle.
In some instances, the bit control parameter may already be at a maximum value, for example when the last conversion cycle was a full bit conversion. If Ai is outside the full scale range of the A/D converter, e.g. due to noise, all available bits will be used until Ai is within range again.
If Ai is within the current bit number range, as determined at block362, the bit control parameter is decreased at block366. A decreased bit control parameter will be used to decrease the adaptable bit number on the next or another subsequent conversion cycle as long as Ai remains within an adapted bit number range. Techniques for controlling how often the adaptable bit number is decreased in response to Ai being within a current bit number range are described in greater detail in conjunction with
After decreasing the bit control parameter, the A/D converter process returns to block355to generate Mout equal to the Mi result of the adapted bit number conversion cycle. As long as Ai is determined to be within the adapted bit number range, the value of Mi converged upon at the end of the shortened binary search is deemed a valid digital value of Ai. Minitial is set for the next conversion cycle, e.g. using Mi, at block356.
The adaptable bit number is set at block358. The adapted bit number may remain the same for a desired number of cycles before decreasing the bit number in response to Ai being within the adapted bit number range. For example, the bit number may be decreased every Zth cycle if Ai has been within adapted bit number range for Z conversion cycles. Alternatively, the bit number may be reduced each time Ai is within an adapted bit number range. A faster reduction of the adaptable bit number may result in more frequent full bit conversions due to Ai being out of range of an adapted bit number. However, too slow of a reduction in the adaptable bit number may limit the benefit of reduced conversion time. Accordingly, the rate that the adaptable bit number is reduced may be optimized to strive for a maximum reduction in overall conversion time and this rate may be automatically adjusted by the A/D converter as well.
After performing a full bit conversion for the first sample point at block404, the first approximation Minitial for the next conversion cycle may be set to the first digitized value Mout at block406, i.e. to the result of the previous conversion cycle performed at block404. The number of bits used for the next conversion is set by the ASAR logic according to a bit control parameter provided by the conversion control module at block408. Computation of the bit control parameter (BIT CONTROL) by the conversion control module is described in greater detail below. ASAR logic sets the number of bits (BIT#) used by the ASAR bit register during the next conversion cycle based on the bit control parameter. In one example, BIT# is set by rounding BIT CONTROL down to the nearest integer (INT(BIT CONTROL)) as shown in the example at block408.
After setting the initial approximation Minitial equal to the previous Mout at block406and setting the adapted bit number at block408, the next conversion cycle begins at block410. A bitbybit binary search may be performed until all bits of the adapted bit number are converted. If all bits of the adapted bit number have not yet been converted, as determined at decision block412, successive approximations of A_{i}, beginning with Minitial, are compared to the current analog signal sample A_{i}at block414. If the approximation Mi is greater than A_{i}for the current bit comparison (decision block414), the successive approximation M_{i}is increased from its current value by an increment (INC) associated with the current bit value, e.g. half the current bit value, at block416.
At block418, a counter included in the ASAR logic is increased by one. This counter may be referred to as a “successive approximation counter” because it is used to count the number of times the approximation M_{i}of Ai is repeatedly and sequentially adjusted in the same direction, i.e., successively increased or successively decreased. As described below, this count is used by the conversion control module to control when the adaptable bit number is increased to the maximum number of available bits. The current bit value will be set to digital high when Ai is greater than the current approximation Mi.
If the current approximation M_{i}is less than A_{i}(decision block414), the approximation M_{i}used for the next comparison is decreased at block420from its current value by a decrement (DEC) associated with the current bit value, e.g. half the current bit value. The current bit value will be set to digital low. The successive adjustment count is decreased by one at block422when the approximation Mi is decreased.
If the approximation M_{i}is repeatedly increased on successive bit conversions, the count will reach the BIT# at block418. In other words, if Ai is greater than Mi for every comparison during the bitbybit binary search, the successive approximations of Mi will all be increased, resulting in the count reaching the bit number. Similarly, if the approximation M_{i}is successively decreased on every bit conversion during the bitbybit binary search, the count will reach the negative value of the bit number at block422. If the approximation of M_{i}is increased on at least one bit conversion and decreased on at least one bit conversion during the current conversion cycle, the count will reach a value less than the bit number.
After all bits are converted, as determined at block412, the absolute value of the successive approximation counter is compared to the bit number at block430. If the absolute value of the count has reached the bit number, indicating the conversion required sequentially increasing successive approximations Mi for every bit or sequentially decreasing successive approximations Mi for every bit, a full bit conversion is performed at block436. Successively increasing approximations or successively decreasing approximations for all bit comparisons indicates Ai is outside the adapted bit number range. A full bit conversion is performed because the signal sample A_{i}is out of the range of the current bit number, in either the positive or negative direction. The full bit conversion at block436allows a digitized representation of A_{i}to be obtained within the full scale range of the A/D converter. The output Mout of the full bit conversion becomes the initial approximation Minitial for the next conversion cycle upon returning to block406.
In response to performing the full bit conversion due to the adapted bit number range not encompassing the ith signal sample A, the conversion control module increases the bit control parameter at block438. The amount P that the bit control parameter is increased in response to a full bit conversion may vary between embodiments and may be a programmable or adjustable number. In one example, BIT CONTROL is increased by one. In this way, each time an out of range condition is reached as indicated by the successive approximation counter reaching the bit number, BIT CONTROL is increased by one thereby increasing the bit number by one for the next conversion cycle. This allows the adjustable bit number to be rapidly increased on succeeding conversion cycles until the bit number range includes the incoming analog signal or the maximum available number of bits is reached.
In some embodiments, the amount P that the bit control parameter is increased at block438is a fixed value. Alternatively, the amount P that BIT CONTROL is increased at block438may be scaled or adapted in response to the output of the full bit conversion performed at block436. For example, the output Mout of the full bit conversion may be compared to previous Mout values. If there is a relatively large difference between Mout for the full bit conversion and the previous Mout value, the bit control parameter may be increased by more than one to cause the ASAR logic to increase the bit number more quickly for a more rapidly varying signal. The difference between Mout for the current conversion cycle and a previous conversion cycle may be compared to a threshold, range, or the bit resolution for determining the increment P applied to the bit control parameter. Generally, if sequential Mout values indicate a relatively high slope of Vin, the bit control parameter may be increased by a greater increment that when sequential Mout values indicate a relatively lower slope of Vin.
After adjusting the bit control parameter at block438, the A/D conversion process returns to block406to set Minitial for starting the next conversion cycle. Minitial may be set to the output Mout of the full bit conversion performed at block436. The bit number for the next conversion cycle is set to the integer value of the bit control parameter at block408. The next conversion cycle starts at block410and proceeds as described previously.
If the absolute value of the successive approximation counter is not equal to the bit number at the end of a conversion cycle, as determined at block430, the conversion is deemed complete by the conversion control module. The digitized value of the final approximation M_{i}generated by the ASAR is received by the conversion control module and produced as the Mout signal provided to the IMD processor and control module (or other control or processing circuitry) from the A/D converter. A count less than the bit number indicates the adapted bit number search converged on a value of Ai within the range of the adapted bit number.
At block434, BIT CONTROL is decreased. The amount by which BIT CONTROL is decreased may vary between embodiments and may be a fixed or adjustable number. In the example shown, the bit control parameter is reduced from its current value by 1/Z where Z may be a fixed or programmable number. Z may alternatively be an automatically adjustable number. For example, IMD10may be configured to “learn” an optimal value for Z for minimizing conversion time for a given analog input signal for a given patient. Z may be any value greater than zero and will typically be, without limitation, an integer value greater than or equal to one.
After adjusting the bit control parameter, the A/D conversion process returns to block406to set Minitial for the next conversion cycle to the most recent digitized value of Ai (provided as Mout) at block432. The bit number for the next conversion cycle is set to the integer value of the bit control parameter. Accordingly, if a fractional portion 1/Z has been subtracted from the previous BIT CONTROL value, the BIT CONTROL value is rounded down to the nearest integer to set the adjusted bit number. The next conversion cycle begins at block410using the initial approximation Minitial and BIT# set at block406and408respectively.
The value of Z is used by the conversion control module to control how frequently the bit number is decreased. For example, when Z is greater than or equal to one, assuming no intervening full bit conversions are required that would cause an increase in the BIT CONTROL at block438, the BIT CONTROL is reduced by 1/Z on each successive conversion cycle. If BIT CONTROL is reduced by 1/Z for Z sequential conversion cycles, BIT# will be reduced by one on the Zth conversion cycle. As such, if Z is equal to or greater than 1, the maximum frequency that the bit number is decreased at block408is every Zth conversion cycle.
In instances that Z is greater than 1 and P is equal to 1, the BIT CONTROL parameter causes the adapted bit number to increase relatively more rapidly in response to an outofrange result of a conversion cycle and decrease relatively less rapidly when the conversion remains within range of the adapted bit number. Reducing the bit time required for a conversion cycle by using an adapted bit number reduces the total power consumption required for A/D conversion. Even though a conversion cycle may need to be repeated using all available bits in response to the successive approximation counter reaching the bit number, the overall conversion time may still be reduced since a full range conversion is not performed for every single conversion cycle.
The bit control divisor Z is plotted along the xaxis504. The divisor Z is used to decrement the bit control parameter in the equation BIT CONTROL=BIT CONTROL−1/Z, as described in conjunction with block434of
Z may be a fixed or adjustable value in various examples. The value selected for Z may be different for different signals being converted by an A/D converter included in IMD10. Depending on the analog signal behavior and other factors, the optimal Z for achieving the greatest reduction in bit time compared to a full bit conversion on every cycle may vary between signal type, sampling rates, between patients, and over time due to other factors influencing the analog signal. Accordingly, Z may be an adjustable value. In some embodiments, the IMD10may store bit time data for varying values of Z to “learn” the optimal value of Z for reducing average bit time for converting a given signal. The optimal Z may be automatically set by the IMD10.
After performing the first conversion cycle, the initial approximation Minitial for the next conversion cycle is set at block608. Minitial for the next conversion cycle may be set based on the digital output value Mout of at least one previous conversion cycle as described above. At block610, the bit number is set for the next conversion cycle, which may be an adapted bit number based on Ai being within an adapted bit number range for a predetermined number of previous conversion cycles as described above.
At612, the initial approximation Minitial is compared to Ai for the current conversion cycle. In some examples, this comparison is made by determining a difference between Ai and Minitial and determining the sign, either positive or negative, of this difference. The sign of the difference Ai−Minitial indicates if Ai is greater than Minitial (a positive difference) or if Ai is less than Minitial (a negative difference). The sign of this difference is used during the adapted bit number conversion cycle because it indicates the direction to adjust the next digital approximation of Ai. If the sign is positive, the next approximation will be increased, and if the sign is negative the next approximation will be decreased.
At block614, Ai is compared to the boundary value of the adapted bit number range in the direction of the sign determined at block612. For example, if the adapted bit number range is ±5 mV, and Ai is determined to be greater than Minitial (a positive sign difference), Ai is compared to the positive or upper boundary of the adapted bit number range, +5 mV in this example. If Ai is less than Minitial, resulting in a negative difference at block612, Ai is compared to the negative or lower boundary of the adapted bit number range.
If Ai exceeds a boundary value of the adapted bit number range, i.e. is either greater than an upper boundary or less than a lower boundary as determined by the comparison at block614, the bit control parameter is increased at block618. A full bit conversion is performed at block604immediately, prior to completing the adapted bit number conversion cycle. If Ai does not exceed a boundary value, i.e. is not greater than an upper boundary or less than a lower boundary, the A/D converter proceeds with completing the adapted bit number conversion at block616. The bit control parameter is decreased at block620for use in setting the bit number in the next conversion cycle.
By comparing Ai to a boundary value after an initial comparison to Minitial, an earlier determination of an outofrange condition is detected than when the successive adjustment counter is used as described in conjunction with in
At block704, a control parameter SIGNinitial is determined as the sign of the difference between Ai and the initial approximation Minitial. If Ai is greater than Minitial, SIGNinitial is set to a value indicating a positive difference, e.g. +1. If Ai is less than Minitial, SIGN is set to a value indicating a negative difference, e.g. 0. The control parameter SIGN will be held at this value corresponding to the polarity of the difference between Ai and Minitial for the complete conversion cycle.
If all bits for the current conversion cycle have not yet been converted, as determined at decision step706, the next digital approximation M_{i+1}is set at block708by adjusting the current approximation Mi (which will be Minitial if the first adjustment is being made in the current conversion cycle). Mi is adjusted in the direction of the polarity of Ai−Mi to obtain the next digital approximation M_{i+1}. For the first comparison in the conversion cycle, the initial approximation Minitial is adjusted in the direction of SIGNinitial to obtain the next M_{i+1}. For example, if SIGN indicates Ai is greater than the initial approximation Minitial, Minitial is increased by the next bit value at block708to obtain M_{i+1}. If Ai is less than the initial approximation Minitial, Minitial is decreased by the next bit value.
Mi is increased from the initial approximation by a positive increment if SIGNinitial is positive by keeping the most significant bit at a logical high value and setting the next most significant bit to a logical high value. Mi is decreased from the initial approximation if SIGNinitial is negative by the negative value of the next bit, e.g. by setting the most significant bit value to a logical low value and setting the next most significant bit to a logical high value.
The value of SIGNinitial set at block704 (based on the difference between Ai and Minitial) is compared to the sign of the difference between Ai and the adjusted approximation M_{i+1}at decision block710. If the difference Ai−M_{i+1}still has the same sign as Ai−Minitial, an affirmative result of the comparison made at block710, the successive adjustment counter is increased by one at block712. The successive adjustment counter counts the number of times the approximation Mi is adjusted in the same direction as SIGNinitial during the conversion cycle. If the sign of the difference between Ai and the next approximation M_{i+1}is different than SIGNinitial, the COUNT is not adjusted (a negative result of decision block710). Accordingly, COUNT is only increased when a bit comparison produces a sign of the difference between Ai and a digital approximation that is the same as SIGNinitial. The COUNT represents the number of bit comparisons that resulted in adjusting Mi in the same direction as SIGNinitial.
Generally, COUNT or another analogous control parameter is determined that represents the number of times Ai was greater than the test signal representing Mi or the number of times Ai was less than the test signal representing Mi during a conversion cycle. If Ai was always greater than or always less than Mi for every comparison during a conversion cycle, Ai is likely out of range of the adapted bit number.
A change in the sign of the difference between Ai and a next successive approximations M_{i+1}relative to SIGNinitial indicates that Ai is within the adapted bit number range being used on the current conversion cycle. The search process is converging on a digital value of Ai within the adjusted bit number range.
The A/D converter returns to block706to set a next approximation M_{i+1}by increasing or decreasing the current Mi in the direction of the sign of the difference between Ai and the current Mi. A sign comparison is made at block710and this process continues until all bits are converted. If, for each bit comparison, Mi is always adjusted in the same direction as SIGNinitial to set the next approximation M_{i+1}, COUNT will reach the adapted bit number for the current conversion cycle, as determined at block730.
In response to the COUNT after all bits are converted, the conversion control module determines whether the conversion cycle is complete or if a full bit conversion is needed due to an outofrange value of Ai. If COUNT has reached the adjusted bit number, as determined at decision block730, a full bit conversion is performed at block736to determine a digital value of Ai. If COUNT has not reached the adjusted bit number, the conversion cycle is complete (block732). The final value of Mi is provided as the digital output value Mout.
The BIT CONTROL parameter is appropriately adjusted at block734or block738. The operations performed by the conversion control module at blocks732, 734, 736, and738correspond to the operations performed at blocks432, 434, 436and438described in conjunction with
After adjusting the BIT CONTROL parameter, the adaptable bit number for the next conversion cycle is set at block740, e.g. as described above in conjunction with
If COUNT has not reached the adapted bit number for the conversion cycle just ending, the BIT CONTROL parameter is decreased because a COUNT less than the adapted bit number is an indication that Ai is within the adapted bit number range for the conversion cycle just ending. At least one successive approximation was adjusted in a direction opposite SIGNinitial. The adapted bit number may be decreased on a subsequent conversion cycle, e.g. when Ai is converged upon within an adapted bit number range for a predetermined number of conversion cycles as described previously herein.
After setting the bit number based on the BIT CONTROL parameter at block740, the process returns to block702where the conversion control module sets the initial approximation for the next conversion cycle. The next conversion cycle begins with the comparison at block704and will proceed using the adapted number of bits set at block740.
AFC802is an Nbit converter configured to receive the analog input signal Vin801and a reference voltage signal804. AFC802includes 2^{N}−1 comparators812athrough812n, collectively812. The voltage signal Vref804is divided to provide an input test signal806athrough806n, collectively806, to each of the comparators812. In the example shown, AFC802includes resistors810athrough810n, collectively810, to provide a resistordivided test signal806to each of the comparators812. Capacitivedivided reference signals may be used instead of resistordivided signals in some examples. The test signal806provided to a respective comparator812corresponds to a digital signal that is one least significant bit greater than the test signal806for the next comparator812immediately below it.
The comparators812are highspeed comparators that operate simultaneously to provide 2^{N}−1 outputs814athrough814n, collectively814, based on the comparisons between Vin801and the respective comparator test signals806. Each comparator812produces a logical high output signal814when the analog input signal Vin801is higher than the respective test signal806. If Vin801is less than the test signal806, the comparator output signal814is 0.
For example, if AFC802is configured to have a full scale range of 5 bits, 31 comparators812will produce a 1 or 0 output signal814based on the comparison between Vin801and the respective resistancedivided test signal806. If Vin801has an amplitude between the 8^{th}and 9^{th}test signals806, provided as input to the respective 8^{th}and 9^{th}comparators, comparators X(1) through X(8), produce logical high output signals814and the remaining comparators X(9) through X(31) produce logical low output signals. The first comparator812producing an output signal814that is logical low indicates the point at which Vin801becomes smaller than the resistancedivided test signal806.
A decoder808receives the comparator output signals814and decodes the 2^{N}−1 logic signals to an Nbit digital word Mi816, the digitized value of Vin801. Decoder808may additionally provide a COUNT818of the number of comparator output signals814that were logical low (zeros) and/or the number of comparator output signals814that were logical high (ones). The COUNT818is an indication of whether Vin was within an adapted bit range of AFC802.
In the illustrative embodiments described herein, binary weighted conversions are performed. It is recognized, however, that nonbinary weighted conversions may be performed that include the techniques for setting an adapted number of comparisons performed per conversion cycle as disclosed herein.
Conversion control module820determines if the current conversion cycle is complete in response to COUNT818and/or Mi816. If the current conversion cycle is complete, conversion control module820provides a digital output signal Mout830. As further described in conjunction with the flow chart of
At block906, the conversion control module820sets Minitial for the next conversion cycle to Mout (or another value based on the results of one or more previous conversion cycles). At block908, conversion control module820and AFC802set the number of comparisons that will be performed on the next conversion cycle. The number of comparisons is adjusted based on the BIT CONTROL parameter. In one example, a range of comparisons made on the next conversion cycle is set based on Minitial, set at block906, and the BIT CONTROL parameter. BIT CONTROL may be decreased each time Vin is within range of an adjusted number of comparisons, as will be described below, and increased in response to Vin being outofrange of an adjusted number of comparisons.
In the example shown in
The adjustment made to set an adapted number of comparisons may be executed by directly adjusting the number of comparators enabled on a current conversion cycle. By adjusting the number of comparators, a fractional bit conversion may be performed as described in greater detail below. Alternatively, the number of bits used for the next conversion cycle may be set to a whole number. The comparators corresponding to the adapted whole bit number may be enabled.
At block912, the flash conversion is performed over the adapted range set at block908, using an adapted number of comparisons. The output Mi816of the flash conversion is provided to conversion control module820. Conversion control module820determines if Vin was within the range of the adapted number of comparisons at decision block914. This determination may be made based on Mi reaching a boundary value of the adapted range. Alternatively, the number of comparators producing a logical high output and/or the number of comparators producing a logical low output may be counted and provided to the conversion control module as COUNT818. The A/D converter determines a proportion of the enabled comparators producing equivalent output signals (ones or zeros) and adjusts the adaptable number of comparisons used for a subsequent conversion cycle in response to the proportion.
To illustrate, COUNT may be the number of comparators producing a logical high output. If COUNT is equal to the adapted number of comparisons, all of the adapted number of comparators206produced a logical high value. A COUNT equal to the adapted number of comparisons indicates Vin801is greater than the test signal806provided to each respective one of the adapted number of comparators812used on the current conversion cycle. This result indicates Vin801is greater than the range of the adapted number of comparisons, i.e. an outofrange value.
If COUNT is the number of comparators producing a logical high output and is equal to zero, all of the adapted number of comparators produced a logical low output. This result indicates Vin801is less than the test signal806provided to each respective comparator812. Vin801is less than the range of the adapted number of comparisons, i.e. an outofrange value. Conversely, a COUNT that is greater than 0 and less than the adapted number of comparisons indicates Vin801is within the adapted RANGE.
If conversion control module820determines Vin is within the adapted range at block914, the BIT CONTROL parameter is decreased at block916. Mout830is set equal to the output Mi of the AFC802at block918. The current conversion cycle is complete. The process returns to block906to start the next conversion cycle by setting the initial digital approximation of the next Vin signal sample equal to Mout830.
If conversion control module820determines Vin is outside the adapted range, the current conversion cycle is not complete. A full bit conversion is performed at block920by enabling an increased number of comparators, e.g. all available comparators using the full scale range of AFC802. The BIT CONTROL parameter is increased at block922in response to Vin being outside the adapted range. The digital output Mout830is set equal to the result of the full bit conversion performed at block920. The process returns to block906to start the next conversion cycle.
BIT CONTROL may be increased by a predetermined increment P, which may be set to one or more, for example, to cause the next conversion cycle to use an adapted number of comparisons corresponding to a bit number that is at least one greater than the previous conversion cycle that resulted in an outofrange condition. In other embodiments P may be a fractional number that causes the number of comparisons to be increased without necessarily increasing the adapted bit number by one whole bit.
At block916, BIT CONTROL may be reduced by 1/Z where Z is a predetermined number that establishes the number of conversion cycles that result in an inrange condition required before reducing the adapted number of comparisons. The integer value of BIT CONTROL may be used to set the number of bits. The number of bits set according to the integer value of BIT CONTROL is used to set the number of comparators enabled in the RANGE=Minitial±2^{BIT CONTROL}. For example, a full scale range of AFC208may be 9 bits. If BIT CONTROL has been previously set to 5 for the current conversion cycle, the conversion is performed using 5 bits, with 31 comparators enabled to produce an output. The outputs of the 31 comparators are decoded to a 5 bit word. If the result of the current conversion cycle is within the adapted range, BIT CONTROL is reduced by 1/Z at block916. If Z is 4, BIT CONTROL is reduced from 5 to 4.75. On the next conversion cycle, the roundedup, integer value of BIT CONTROL is used such that 31 comparators (2^{N}−1) will again be used to produce a 5 bit word until the results of at least 4 conversion cycles have been within the adapted 5bit range to cause a BIT CONTROL value of 4, at which point15comparators will be enabled.
Alternatively, a noninteger value of BIT CONTROL may be used to set the number of comparators enabled for the next conversion cycle. Following the illustrative example given above, if BIT CONTROL has been previously set to 5 out of a total of 9 available bits, the current conversion cycle operates using 5 bits, with 31 comparators enabled to produce a digital output. If the result of the current conversion cycle is within the adapted range, BIT CONTROL is reduced by 1/Z at block916. If Z is 4, BIT CONTROL is reduced from 5 to 4.75. On the next conversion cycle, RANGE may be set to Minitial±2^{4.75}such that the number of comparators (26 comparators) that are enabled at block908is between the total number of comparators used for 4 bits (15 comparators) and the total number of comparators used for 5 bits (31 comparators). Accordingly, in some embodiments, the adapted number of comparisons does not necessarily correspond to a whole number of bits but may include a fractional number of bits. The adapted number of comparisons can be the number of comparators used in the AFC802that may constitute a whole or fractional number of bits.
The conversion control module920may increase BIT CONTROL relatively more rapidly when an out of range result occurs from the current conversion cycle and decrease BIT CONTROL relatively less rapidly when in an inrange result occurs. The BIT CONTROL may be adjusted, for example, to cause the adapted number of comparisons to increase by 8 comparators in response to an outofrange result and decrease by 1 comparator in response to an inrange result.
The bit control divisor Z is plotted along the xaxis1004. The divisor Z is used to decrease the BIT CONTROL parameter in the equation BIT CONTROL=BIT CONTROL−1/Z, as described in conjunction with block916of
As described previously, Z may be a fixed or adjustable value in various examples employing a selfadjusting A/D converter. The value selected for Z may be different for different signals being converted and may depend on the analog signal behavior and other factors. An optimal Z for achieving the greatest reduction in the average number of comparisons compared to a full bit conversion on every cycle may vary between signal type, sampling rates, between patients, and over time due to other factors influencing the analog signal. In some embodiments, the IMD10may store adapted comparison number data for varying values of Z to “learn” the optimal value of Z for reducing the average number of comparisons for converting a given signal. The optimal Z may be automatically set by the IMD10.
Thus, various embodiments of an apparatus and method for A/D conversion have been described. However, one of ordinary skill in the art will appreciate that various modifications may be made to the described embodiments without departing from the scope of the claims. For example, although specific examples of conversion control parameters and parameter values have been described, it is recognized that other control parameters or parameter values may be defined or conceived for controlling an adaptable bit number and an initial approximation of a digital value of an analog signal sample for reducing the average time required for A/D conversion cycles. These and other examples are within the scope of the following claims.