Semiconductor device

• US 8,941,958 B2
• Filed: 04/17/2012
• Issued: 01/27/2015
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tomatsu, Hiroyuki
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Kitov, Zeev V
• Application Number:
  US13/448,496
• Publication Number:
  US 20120268849A1
• Time in Patent Office: 1,015 Days
• Field of Search: 361/56, 361/91.1
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

To provide a protection circuit having a small area, redundancy, and small leak current. In the protection circuit, a plurality of nonlinear elements is provided so as to overlap with each other and so as to be electrically connected in series. At least one nonlinear element in the protection circuit is a diode-connected transistor including an oxide semiconductor in its channel formation region. The other nonlinear element is a diode-connected transistor including silicon in its channel formation region or a diode including silicon in its junction region.

Claims

1. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a first protection circuit comprising;

a first nonlinear element; and

a third nonlinear element over the first nonlinear element, the third nonlinear element being electrically connected to the first nonlinear element in series; and

a second protection circuit comprising;

a second nonlinear element; and

a fourth nonlinear element over the second nonlinear element, the fourth nonlinear element being electrically connected to the second nonlinear element in series,

wherein the first protection circuit is electrically connected between the first wiring and the second wiring so that a forward bias is applied to the first nonlinear element and the third nonlinear element included in the first protection circuit when a potential of the first wiring is higher than a potential of the second wiring,

wherein the second protection circuit is electrically connected between the first wiring and the third wiring so that a forward bias is applied to the second nonlinear element and the fourth nonlinear element included in the second protection circuit when the potential of the first wiring is lower than a potential of the third wiring,

wherein the first nonlinear element and the second nonlinear element include silicon,

wherein the third nonlinear element and the fourth nonlinear element are transistors including an oxide semiconductor in their respective channel formation regions,

wherein the first nonlinear element and the second nonlinear element are transistors including silicon in their respective channel formation regions, and

wherein the transistors are p-channel transistors.

2. The semiconductor device according to claim 1,

wherein the first wiring is a signal line through which a signal is input to a semiconductor circuit,

wherein the second wiring is a first power supply line,

wherein the third wiring is a second power supply line, and

wherein a potential of the first power supply line is higher than a potential of the second power supply line.

3. The semiconductor device according to claim 1, wherein the transistors are diode-connected.

4. A semiconductor device comprising:

a first wiring;

a second wiring;

a protection circuit comprising;

a first transistor including silicon in a channel formation region; and

a second transistor including an oxide semiconductor in a channel formation region, the second transistor being over the first transistor and electrically connected to the first transistor in series,

wherein the protection circuit is electrically connected between the first wiring and the second wiring so that a forward bias is applied to the first transistor and the second transistor included in the protection circuit when a potential of the first wiring is higher than a potential of the second wiring,

wherein the first transistor is a p-channel transistor, and

wherein the second transistor is a n-channel transistor.

5. A semiconductor device comprising:

a circuit;

a first wiring;

a second wiring;

a protection circuit comprising;

a first transistor comprising;

a first channel formation region including silicon;

a first gate electrode;

a first source electrode; and

a first drain electrode;

a second transistor over the first transistor comprising;

a second channel formation region including an oxide semiconductor;

a second gate electrode;

a second source electrode; and

a second drain electrode,

wherein the first wiring is electrically connected to the circuit,

wherein one of the first source electrode and the first drain electrode is electrically connected to the first gate electrode and the second wiring,

wherein one of the second source electrode and the second drain electrode is electrically connected to the second gate electrode and the first wiring,

wherein the other of the first source electrode and the first drain electrode is electrically connected to the other of the second source electrode and the second drain electrode, and

wherein the first transistor is a p-channel transistor.