Nonvolatile memory device and a method of adjusting a threshold voltage of a ground selection transistor thereof
First Claim
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1. A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device, the method comprising:
- providing a first voltage to a gate of a first ground selection transistor in a read operation; and
providing a second voltage to a gate of a second ground selection transistor in the read operation, wherein the nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.
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Abstract
A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.
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Citations
15 Claims
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1. A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device, the method comprising:
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providing a first voltage to a gate of a first ground selection transistor in a read operation; and providing a second voltage to a gate of a second ground selection transistor in the read operation, wherein the nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A nonvolatile memory device, comprising:
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a memory cell array having a plurality of memory blocks, at least one of the memory blocks including at least one string having string selection transistors, memory cells, and first and second ground selection transistors connected in series and formed on a substrate; a read/write circuit configured to read data from or write data to the memory cell array; an address decoder configured to generate a block selection signal in response to an address; a block gating circuit configured to select one of the plurality of memory blocks in response to the block selection signal; and control logic configured to control the read/write circuit, the address decoder, and the block gating circuit, wherein the control logic adjusts a threshold voltage of at least one of the first and second ground selection transistors by providing a first voltage to a gate of the first ground selection transistor and a second voltage to a gate of the second ground selection transistor in a read operation. - View Dependent Claims (14, 15)
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Specification