Method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer

• US 8,942,635 B2
• Filed: 11/15/2013
• Issued: 01/27/2015
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya, Afsahi, Ali, Magoon, Vikram, Gupta, Alok
• Primary Examiner(s): Bilodeau, David
• Application Number:
  US14/080,898
• Publication Number:
  US 20140132346A1
• Time in Patent Office: 438 Days
• Field of Search: 455/63.1
• US Class Current: 455/63.1
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3294 Acting on the real and imaginary components of the input signal
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/57 Separate feedback of real and complex signals being present
• CPC Class Codes: H04L 27/368 adaptive predistortion

Abstract

Aspects of a method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer are presented. Aspects of the system may include at least one circuit that enables generation of an output signal in response to one or more generated input signals. A feedback signal may be generated within a single feedback mixer circuit that may perform a frequency mix-down operation on the generated output signal. The generated feedback signal may be inserted at one or more insertion points in a receiver. Each of the insertion points may be located between a mixer stage of the receiver, and one or more circuits that generate a baseband signal based on the generated feedback signal.

Claims

1. A system implemented in a single chip, comprising:

a feedback mixer circuit configured to perform a frequency mix-down operation on an output signal of a radio frequency (RF) transmitter to generate a feedback signal; and

a plurality of selector switches configured by a processor to insert, during a calibration mode, the generated feedback signal at insertion points in an RF receiver corresponding to in-phase (I) and quadrature-phase (Q) components of the output signal by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points.

2. The system of claim 1, wherein the processor is configured to compensate for at least one of amplitude modulation to amplitude modulation (AM-AM) distortion or amplitude modulation to phase modulation (AM-PM) distortion of the power amplifier utilizing the plurality of selector switches.

3. The system of claim 1, further comprising a signal attenuator configured to attenuate the output signal and transmit the attenuated output signal to the feedback mixer circuit.

4. The system of claim 3, wherein the signal attenuator is configured to attenuate the output signal based on a linear operating range of the feedback mixer circuit.

5. The system of claim 3, wherein the signal attenuator is configured to attenuate the output signal at a level specified by the processor.

6. The system of claim 1, wherein the plurality of selector switches is configured by the processor to disable the closed feedback loop configuration during a normal operating mode.

7. The system of claim 1, wherein the closed feedback loop includes a power amplifier of the RF transmitter.

8. A method, comprising:

generating an output signal of a radio frequency (RF) transmitter in a chip, in response to an input signal;

performing a frequency mix-down operation on the output signal to generate a feedback signal; and

selectively inserting, during a calibration mode, the generated feedback signal at insertion points in an RF receiver in the chip, the insertion points corresponding to in-phase (I) and quadrature-phase (Q) components of the output signal by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points.

9. The method of claim 8, wherein generating the feedback signal is performed across distinct power levels of the input signal.

10. The method of claim 9, further comprising estimating an output power level for each generated output signal based on the corresponding feedback signal for each distinct input power level.

11. The method of claim 10, further comprising estimating amplitude distortion in each generated output signal based on:

the estimated output power level and corresponding input power level.

12. The method of claim 8, comprising performing the frequency mix-down operation on an attenuated version of the generated output signal.

13. The method of claim 12, comprising selecting an attenuation level for generating the attenuated version of the generated output signal.

14. The method of claim 8, comprising selecting a frequency for the frequency mix-down operation.

15. The method of claim 8, wherein the closed feedback loop includes a power amplifier of the RF transmitter.

16. A radio frequency (RF) transceiver in a single chip, comprising:

a feedback mixer circuit configured perform a frequency mix-down operation on an output signal of a RF transmitter to generate a feedback signal; and

a selection circuit in an RF receiver configured to insert the generated feedback signal at a first insertion point and a second insertion point in the RF receiver by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points, wherein the first insertion point corresponds to an output of a first amplifier of the RF receiver and the second insertion point corresponds to an output of a second amplifier of the RF receiver.

17. The RF transceiver of claim 16, wherein a signal attenuator is configured to attenuate the output signal based upon a specified attenuation level.

18. The RF transceiver of claim 16, comprising a processor that configures the selection circuit to insert, during a calibration mode, the generated feedback signal at the first and second insertion points.

19. The RF transceiver of claim 18, wherein the processor is further configured to estimate amplitude distortion in the generated output signal based upon an estimated output power level and a corresponding input power level.

20. The RF transceiver of claim 18, wherein the processor is further configured to estimate phase distortion in the generated output signal based upon an estimated output time instant, an input time instant, and a corresponding distinct input signal level.