Linear device value estimating method, capacitance detection method, integrated circuit, touch sensor system, and electronic device

• US 8,942,937 B2
• Filed: 05/22/2012
• Issued: 01/27/2015
• Est. Priority Date: 06/27/2011
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Miyamoto, Masayuki, Iizuka, Kunihiko
• Primary Examiner(s): Bui, Bryan
• Assistant Examiner(s): SUAREZ, FELIX E
• Application Number:
  US14/128,907
• Publication Number:
  US 20140149059A1
• Time in Patent Office: 980 Days
• Field of Search: 702/65, 702/85, 702/150, 702/155, 702/189, 702/194, 178/18.02, 345/174
• US Class Current: 702/65
• CPC Class Codes: G06F 2203/04104 Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A capacitance distribution detection circuit includes a multiplexer, a driver, and a sense amplifier. The multiplexer switches states between a first connection state and a second connection state. The first connection state drives first signal lines in parallel so that voltages are applied, outputs, along second signal lines, a linear sum of electric charges stored in capacitors corresponding to that respective one of the second signal lines, and estimates, a capacitance of capacitors formed along that second signal line. The second connection state drives, the second signal lines in parallel so that voltages are applied, outputs, along the first signal lines, a linear sum of electric charges stored in the capacitors corresponding to that respective one of the first signal lines, and estimates, a capacitance of the capacitors formed along that first signal line.

Claims

1. A method of estimating a linear device value, to detect a distribution of values of a plurality of linear devices that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines,

the method comprising the steps of:

driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections outputs that correspond to the linear devices, wherein the first signal lines are connected to the drive sections and the second signal lines are connected to estimation sections;

controlling, with use of a multiplexer, in a second timing subsequent to the first timing, a switching of connections of the first signal lines with that of the second signal lines so that the first signal lines are connected to the estimation sections and the second signal lines are connected to the drive sections; and

driving, in the drive sections, the second signal lines in a third timing subsequent to the second timing, to output from the first signal lines to the estimation sections the outputs that correspond to the linear devices,

the step of driving the first signal lines comprising;

(A) (a) driving, on a basis of code sequences di, the plurality of first signal lines in parallel, and thus (b) outputting, along each of the plurality of second signal lines, a linear sum of the outputs of the linear devices corresponding to that respective one of the plurality of second signal lines; and

(B) estimating, on a basis of an inner product operation of (i) the linear sum outputted along the respective second signal line and (ii) the code sequences di, a value of the linear devices disposed along that second signal line, for each of the plurality of second signal lines, and

the step of driving the second signal lines comprising;

(C) (a) driving, on a basis of the code sequences di, the plurality of second signal lines in parallel, and thus (b) outputting, along each of the plurality of first signal lines, a linear sum of the outputs of the linear devices corresponding to that respective one of the plurality of first signal lines; and

(D) estimating, on a basis of an inner product operation of (i) the linear sum outputted along the respective first signal line and (ii) the code sequences di, a value of the linear devices provided along that first signal line, for each of the plurality of first signal lines.

2. The linear device estimating method according to claim 1, wherein the code sequences di include elements each being either +V or −

V.

3. A method of detecting capacitance, to detect a distribution of capacitance of a plurality of capacitors that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines,

the method comprising the steps of:

driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections electric charges that correspond to the capacitors, wherein the first signal lines are connected to the drive sections and the second signal lines are connected to estimation sections;

controlling, with use of a multiplexer, in a second timing subsequent to the first timing, a switching of connections of the first signal lines with that of the second signal lines so that the first signal lines are connected to the estimation sections and the second signal lines are connected to the drive sections; and

driving, in the drive sections, the second signal lines in a third timing subsequent to the second timing, to output from the first signal lines to the estimation sections the electric charges that correspond to the capacitors,

the step of driving the first signal lines comprising;

(A) (a) driving, on a basis of code sequences di which include elements each being either +1 or −

1, the plurality of first signal lines in parallel, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −

V is applied for an element of −

1 in the code sequences, and thus (b) outputting, along each of the plurality of second signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of second signal lines; and

(B) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective second signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that second signal line, for each of the plurality of second signal lines, and

the step of driving the second signal lines comprising;

(C) (a) driving, on a basis of the code sequences, the plurality of second signal lines in parallel, so that a voltage +V is applied for the element of +1 in the code sequences and that a voltage −

V is applied for the element of −

1 in the code sequences, and thus (b) outputting, along each of the plurality of first signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of first signal lines; and

(D) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective first signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that first signal line, for each of the plurality of first signal lines.

4. A method of detecting capacitance, to detect a distribution of capacitance of a plurality of capacitors that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines,

the method comprising the steps of:

driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections electric charges that correspond to the capacitors, wherein the first signal lines are connected to the drive sections and the second signal lines are connected to estimation sections;

controlling, with use of a multiplexer, in a second timing subsequent to the first timing, a switching of connections of the first signal lines with that of the second signal lines; and

driving, in the drive sections, the second signal lines in a third timing subsequent to the second timing, to output from the first signal lines to the estimation sections the electric charges that correspond to the capacitors,

the step of driving the first signal lines comprising;

(A) (a) driving, on a basis of code sequences di which include elements each being either +1 or −

1, the plurality of first signal lines in parallel, and thus (b) outputting, to analog integrators of the estimation sections, along each of the plurality of second signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of second signal lines; and

(B) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective second signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that second signal line, for each of the plurality of second signal lines, and

the step of driving the second signal lines comprising;

(C) (a) driving, on a basis of the code sequences, the plurality of second signal lines in parallel, and thus (b) outputting, to the analog integrator, along each of the plurality of first signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of first signal lines; and

(D) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective first signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that first signal line, for each of the plurality of first signal lines,

the step (A), for an element of +1 in the code sequences, driving the plurality of first signal lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the linear sums of the electric charges outputted along the respective second signal lines are sampled and, for an element of −

1 in the code sequences, driving the plurality of first signal lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the linear sums are sampled.