Latency sensitive software interrupt and thread scheduling

• US 8,943,252 B2
• Filed: 08/16/2012
• Issued: 01/27/2015
• Est. Priority Date: 08/16/2012
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Waters, Bradley M., Zhu, Danyu
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US13/587,737
• Publication Number:
  US 20140052882A1
• Time in Patent Office: 894 Days
• Field of Search: 710260-269, 718/100, 718/104, 718/108
• US Class Current: 710/267
• CPC Class Codes: G06F 2209/5021 Priority
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/505 considering the load

Abstract

Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.

Claims

1. A computer-implemented method comprising:

receiving a software interrupt;

responsive to receiving the software interrupt, determining whether the software interrupt is latency sensitive;

responsive to determining the software interrupt is latency sensitive, determining whether a current processor core is interrupt heavy;

responsive to determining the current processor core is interrupt heavy and that the software interrupt is latency sensitive, determining a desired processor core other than the current processor core to run the software interrupt; and

responsive to determining the desired processor core other than the current processor core, executing the software interrupt on the desired processor core.

2. The method of claim 1 further comprising:

responsive to determining the current processor core is not interrupt heavy, executing the interrupt on the current processor core.

3. The method of claim 1, wherein the determining whether the software interrupt is latency sensitive further comprises analyzing a data structure associated with the software interrupt.

4. The method of claim 3, wherein the data structure is configured to include a latency-sensitive flag to indicate whether the software interrupt is latency-sensitive or not.

5. The method of claim 4, wherein the determining a current processor core is interrupt heavy comprises analyzing a second data structure.

6. The method of claim 1, wherein the determining a desired processor core other than the current processor core further comprises identifying a processor core less loaded than the current processor core.

7. The method of claim 1 further comprising:

identifying the desired processor core based, at least in part, on the desired processor core not being interrupt-heavy.

8. The method of claim 1, wherein the software interrupt is associated with an input device.

9. One or more computer readable storage devices embodying computer readable instructions which, when executed, implement a method comprising:

preparing a software thread to run;

determining whether the software thread is latency-sensitive;

responsive to determining the software thread is latency-sensitive, gathering processor core usage information;

determining a desired processor core to run the software thread based, at least in part, on the processor core usage information; and

responsive to determining the desired processor core, running the software thread on said determined processor core.

10. The one or more computer readable storage devices of claim 9, wherein the software thread comprises a software thread associated with a software application.

11. The one or more computer readable storage devices of claim 9, wherein the processor core usage information comprises a percentage of usage of the processor core.

12. The one or more computer readable storage devices of claim 9, wherein the gathering processor core usage information further comprises:

identifying whether a usage value associated with a current processor core has exceeded a usage threshold; and

responsive to identifying the usage value associated with the current processor core has exceeded the usage threshold, assigning the software thread to the desired processor core.

13. The one or more computer readable storage devices of claim 9, wherein the method further comprises:

responsive to determining the software thread is not latency-sensitive, executing the software thread on a pre-assigned processor core.

14. A system comprising:

one or more processor cores;

one or more computer-readable storage media associated with the one or more processor cores;

one or more processor core loading modules configured to;

identify whether a task is latency-sensitive or not;

identify one or more characteristics associated with the one or more processor cores; and

assign the task to a processor core with available resources based at least in part, on whether the task is latency-sensitive or not and based, at least in part, on the one or more characteristics associated with the one or more processor cores.

15. The system of claim 14, wherein the one or more processor core loading modules are further configured to:

periodically gather metrics associated with the one or more processor cores; and

update one or more data structures based, at least in part, on gathered metrics.

16. The system of claim 15, wherein the metrics comprise processor core usage percentages.

17. The system of claim 15, wherein the one or more processor core loading modules are further configured to periodically gather metrics based upon a clock tick associated with a processor core.

18. The system of claim 14, wherein the one or more processor core modules are further configured to reassign the task to a different processor core when an originally assigned processor core has been determined as being interrupt heavy.

19. The system of claim 14, wherein the one or more processor core modules are further configured to assign tasks to processor cores based, at least in part, on a total system metric goal associated with total processor usage.

20. The system of claim 14, wherein the task comprises a software interrupt.