Controlling a turbo mode frequency of a processor
First Claim
Patent Images
1. A method comprising:
- analyzing, in a logic of a multicore processor including a plurality of cores, a plurality of power state change events during an evaluation interval to determine a hypothetical number of frequency transitions responsive to the plurality of power state change events for each of N-core turbo frequencies;
selecting one of the N-core turbo frequencies to be a maximum operating frequency of the multicore processor for a next operating interval based at least in part on the hypothetical number of frequency transitions, the selected N-core turbo frequency less than a configured maximum operating frequency of the multicore processor; and
controlling the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval.
2 Assignments
0 Petitions
Accused Products
Abstract
In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
126 Citations
20 Claims
-
1. A method comprising:
-
analyzing, in a logic of a multicore processor including a plurality of cores, a plurality of power state change events during an evaluation interval to determine a hypothetical number of frequency transitions responsive to the plurality of power state change events for each of N-core turbo frequencies; selecting one of the N-core turbo frequencies to be a maximum operating frequency of the multicore processor for a next operating interval based at least in part on the hypothetical number of frequency transitions, the selected N-core turbo frequency less than a configured maximum operating frequency of the multicore processor; and controlling the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A processor comprising:
-
a plurality of cores to independently execute instructions; and a power controller to control a frequency at which the processor is to operate, the power controller to limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, wherein the power controller is to analyze a plurality of power state change events during an evaluation interval to determine a hypothetical number of frequency transitions for each of N-core turbo frequencies, select one of the N-core turbo frequencies to be the maximum operating frequency for a next operating interval based at least in part on the hypothetical number of frequency transitions, the selected N-core turbo frequency less than the configured maximum operating frequency, and control the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. An article comprising a machine-accessible non-transitory storage medium including instructions that when executed cause a controller of a multicore processor to:
-
responsive to a power state change event of at least one core of a multicore processor having a plurality of cores, determine a number of cores of the multicore processor to be in an active state after the power state change event; and determine whether to update a first entry of a turbo demotion table associated with a N-core turbo frequency based at least in part on whether a frequency transition would be performed if the multicore processor were operating at the N-core turbo frequency. - View Dependent Claims (17, 18, 19, 20)
-
Specification