Semiconductor device reliability model and methodologies for use thereof

• US 8,943,444 B2
• Filed: 06/20/2013
• Issued: 01/27/2015
• Est. Priority Date: 06/20/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Habib, Nazmul, Li, Baozhen, Nsame, Pascal A., Bickford, Jeanne P.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US13/922,311
• Publication Number:
  US 20140380261A1
• Time in Patent Office: 586 Days
• Field of Search: 716/55, 716/126, 716/139
• US Class Current: 716/55
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Claims

1. A method comprising:

generating an aggregate reliability model using a manufacturing line distribution, wherein the aggregate reliability model is generated using reliability failure mechanisms;

selecting a line center within a process window of the aggregate reliability model;

assigning a percentage of the manufacturing line distribution to each performance process window bin within the process window;

calculating a product fail rate for each of the performance process window bins, wherein the calculating the product fail rate comprises setting different fail rates for each of the reliability failure mechanisms as a function of the performance process window for each performance process window bin;

calculating a composite fail rate for the manufacturing line distribution based on the percentage of the manufacturing line distribution assigned to each performance process window bin and the product fail rate calculated for each of the performance process window bins;

calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution;

calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution; and

optimizing the line center to minimize the product fail rate for each of the performance process window bins, wherein the optimizing the line center comprises;

comparing the product reliability fail rate to a manufacturing line centering fail rate;

determining whether the product reliability fail rate meets product reliability requirements;

when the product reliability fail rate does not meet product reliability requirements, reevaluating the reliability failure mechanisms and selecting at least one new reliability failure mechanism;

identifying a process point within the process window that has a lower fail rate for the new reliability failure mechanism; and

repeating the steps of selecting the line center, assigning the percentage of the manufacturing line distribution, and calculating the product fail rate using a newly selected line center and the new reliability failure mechanism; and

wherein at least the step of generating the aggregate reliability model is performed using a processor.

2. A method comprising:

generating an aggregate reliability model using a manufacturing line distribution, wherein the aggregate reliability model is generated using reliability failure mechanisms;

selecting a line center within a process window of the aggregate reliability model;

assigning a percentage of the manufacturing line distribution to each performance process window bin within the process window;

calculating a product fail rate for each of the performance process window bins, wherein the calculating the product fail rate comprises setting different fail rates for each of the reliability failure mechanisms as a function of the performance process window for each performance process window bin;

calculating a composite fail rate for the manufacturing line distribution based on the percentage of the manufacturing line distribution assigned to each performance process window bin and the product fail rate calculated for each of the performance process window bins;

calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution;

calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution and optimizing the line center to minimize the product fail rate for each of the performance process window bins, wherein the optimizing the line center comprises;

comparing the product reliability fail rate to a manufacturing line centering fail rate;

determining whether the product reliability fail rate meets product reliability requirements; and

utilizing a process flow to ensure that a best center line is selected to optimize the product reliability fail rate meeting the product reliability requirements, wherein the process flow includes a search to find values of an objective function given a defined domain including a variety of different types of objective functions and different types of domain; and

wherein at least the step of generating the aggregate reliability model is performed using a processor.

3. A method comprising:

generating an aggregate reliability model using a manufacturing line distribution of a semiconductor product;

defining performance process window bins of a performance window for an excursion event of the semiconductor product;

determining a fail rate for each of the performance process window bins;

disposing of production shipment for the semiconductor product as a function of the fail rate determined for each of the performance process window bins;

determining whether the semiconductor product is to receive a reliability screen;

when the semiconductor product is not to receive the reliability screen, determining whether the excursion event is impacting reliability of the semiconductor product;

identifying a failure mechanism based on the excursion event that is impacting the calculating a composite fail rate using the failure mechanism;

comparing the composite fail rate to a target reliability; and

when the composite fail rate meets the target reliability, shipping the semiconductor product,

wherein at least the step of generating the aggregate reliability model is performed using a processor.

4. The method of claim 3, further comprising:

when the composite fail rate does not meet the target reliability, using the aggregate reliability model to create a composite aggregate reliability model for each of the performance process window bins based on the excursion event;

determining whether at least one of the performance process window bins meet the target reliability; and

when none of the performance process window bins meet the target reliability, scrapping the semiconductor product.

5. The method of claim 4, further comprising when at least one of the performance process window bins meet the target reliability, identifying portions of the semiconductor product that can be shipped.

6. A method comprising:

generating an aggregate reliability model using a manufacturing line distribution of a semiconductor product;

defining performance process window bins of a performance window for an excursion event of the semiconductor product;

determining a fail rate for each of the performance process window bins;

disposing of production shipment for the semiconductor product as a function of the fail rate determined for each of the performance process window bins;

determining whether the semiconductor product is to receive a reliability screen;

when the semiconductor product is to receive the reliability screen, determining whether the excursion event is impacting reliability of the semiconductor product;

identifying a failure mechanism based on the excursion event that is impacting the reliability;

calculating a composite fail rate using the failure mechanism;

comparing the composite fail rate to a target reliability; and

when the composite fail rate meets the target reliability, shipping the semiconductor product with a standard reliability screen,

wherein at least the step of generating the aggregate reliability model is performed using a processor.

7. The method of claim 6, further comprising:

when the composite fail rate does not meet the target reliability, using the aggregate reliability model to create a composite aggregate reliability model for each of the performance process window bins based on the excursion event;

determining whether at least one of the performance process window bins meet the target reliability with the standard reliability screen; and

when none of the performance process window bins meet the target reliability, identifying an increase in the standard reliability screen, applying the increased standard reliability screen to each of performance process window bins, and shipping the semiconductor product with the increased standard reliability screen.

8. The method of claim 7, further comprising when at least one of the performance process window bins meet the target reliability, identifying portions of the semiconductor product that can be shipped with the standard reliability screen or the increased reliability screen.