Method for forming dummy gate

• US 8,946,030 B2
• Filed: 12/17/2013
• Issued: 02/03/2015
• Est. Priority Date: 12/18/2012
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Noro, Motoki, Lin, Tai-Chuan, Kawada, Shinji
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/109,231
• Publication Number:
  US 20140170842A1
• Time in Patent Office: 413 Days
• Field of Search: 438/585, 438/696
• US Class Current: 438/283
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32192 Microwave generated discharge H01J37/32357, H01J37/32366, H01J37/32394, H01J37/32403 take precedence
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.

Claims

1. A method of forming a dummy gate in manufacturing a field effect transistor, the method comprising:

a first process of exposing a workpiece having a polycrystalline silicon layer formed on an insulating layer and a semiconductor part to microwave-generated plasma of HBr gas and O₂ gas, the first process including etching the polycrystalline silicon layer until the insulating layer and the semiconductor part are exposed to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and at the same time, forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part by supplying a relatively smaller amount of activated species of the HBr gas and O₂ gas to the lower end of the dummy semiconductor part compared to an upper end of the dummy semiconductor part;

a second process of further exposing the workpiece to the microwave-generated plasma of HBr gas and O₂ gas after the insulating layer and the semiconductor part are exposed during the first process thereby laterally etching the dummy semiconductor part along with the protection film formed on the side surfaces thereof such that a taper-shaped dummy semiconductor part is formed at a lower portion of the dummy semiconductor part which is below a top of the semiconductor part; and

a third process of further exposing the workpiece to plasma of bromine gas or plasma of chlorine gas after the second process,

wherein an angle of a corner area formed between the insulating layer and one of the side surfaces on an inside of the dummy semiconductor part is an obtuse angle.

2. The dummy gate forming method according to claim 1, wherein the field effect transistor is a fin type field effect transistor,

the semiconductor part is a fin type semiconductor part and the workpiece includes one or more fin type semiconductor parts,

the polycrystalline silicon layer is provided to cover the one or more fin type semiconductor parts prior to the first process, and

the dummy semiconductor part is formed to extend in a direction intersecting with the one or more fin type semiconductor parts.

3. The method of claim 1, wherein a temperature of the workpiece is set within a range of 60°

C.-70°

C.

4. The method of claim 1, wherein a relative flow rate of the HBr gas to a flow rate of the O₂ gas is controlled to control a height of the taper-shape at the lower portion of the dummy semiconductor part.

5. The method of claim 1, wherein a microwave power is controlled during the second process to control an etching speed such that a height of the taper-shape at the lower portion of the dummy semiconductor part is controlled.

6. The method of claim 5, wherein the microwave power is controlled in a range of 1700 W and 2300 W.

7. The method of claim 1, wherein a time of exposing the workpiece during the second process is adjusted to control an etching amount of the lower portion of the dummy semiconductor part.

8. The method according to claim 1, further including providing a spacer on each side surface of the dummy semiconductor part after the third process with the spacers formed above the insulating layer, and thereafter removing the dummy semiconductor part, and wherein after removal of the dummy semiconductor part an angle between the insulating layer and each spacer at a location between the spacers is an obtuse angle.