Method for fabricating MOS device

• US 8,946,031 B2
• Filed: 01/18/2012
• Issued: 02/03/2015
• Est. Priority Date: 01/18/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Chih-Jung, Chen, Tong-Yu
• Primary Examiner(s): Sengdara, Vongsavanh
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US13/353,227
• Publication Number:
  US 20130183804A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/288, 257/401, 438/151, 438/257
• US Class Current: 438/285
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.

Claims

1. A method for fabricating a MOS device, comprising:

forming a first hard mask layer over a semiconductor substrate;

patterning the first hard mask layer and removing a portion of the substrate to form a first patterned hard mask and a fin structure surrounded by a trench, wherein the fin structure extends in a first direction;

forming an insulating layer at a bottom of the trench;

forming, on the insulating layer in the trench, a gate conductive layer that extends in a second direction;

performing a first implant process with the first patterned hard mask as a mask to form first source/drain extension regions in sidewalls of the fin structure;

removing the first patterned hard mask to expose a top of the fin structure; and

after removing the first patterned hard mask and before forming a spacer on the gate conductive layer, performing a second implant process to form second source/drain extension regions in the top of the fin structure while a sidewall of the gate conductive layer is exposed,

wherein an implant angle of the first implant process is within the range of 30°

to 60°

with respect to a normal line to a surface of the semiconductor substrate on which the gate conductive layer is formed.

2. The method of claim 1, wherein forming the gate conductive layer comprises:

forming a conductive material layer on the insulating layer in the trench;

planarizing the conductive material layer using the first patterned hard mask as a stop layer;

forming a second hard mask layer on the conductive material layer; and

patterning the second hard mask layer and the conductive material layer into a second patterned hard mask and the gate conductive layer, respectively.

3. The method of claim 1, wherein forming the gate conductive layer comprises:

forming a conductive material layer on the insulating layer in the trench;

planarizing the conductive material layer, wherein a top surface of the remaining conductive material layer is higher than a top surface of the first patterned hard mask; and

patterning the conductive material layer into the gate conductive layer.

4. The method of claim 3, further comprising:

forming a first spacer around the gate conductive layer before the first implant process is performed.

5. The method of claim 1, wherein forming the insulating layer comprises:

forming an insulating material over the substrate;

planarizing the insulating material using the first patterned hard mask as a stop layer; and

removing a portion of the insulating material remaining in the trench.

6. The method of claim 1, wherein an implant angle of the second implant process is substantially 90°

with respect to the surface of the semiconductor substrate.

7. The method of claim 1, wherein the first implant process forms the first source/drain extension regions in sidewalls along the first direction of the fin structure.

8. The method of claim 1, wherein an implant angle of the first implant process and the implant angle of the second implant process with respect to a normal line to a surface of the semiconductor substrate on which the gate conductive layer is formed are different.