Controlling the device performance by forming a stressed backside dielectric layer

• US 8,946,084 B2
• Filed: 09/30/2013
• Issued: 02/03/2015
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Lin, I-Ching
• Primary Examiner(s): Blum, David S
• Application Number:
  US14/042,154
• Publication Number:
  US 20140295582A1
• Time in Patent Office: 491 Days
• Field of Search: 438/667, 257/E21.158, 257/E27.062
• US Class Current: 438/667
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Claims

1. A method comprising:

pre-determining a target stress at a selected location in a semiconductor substrate of a wafer;

forming a through-substrate via (TSV) in the selected location;

finding a first stress applied to the selected location by the TSV;

selecting a material and process conditions for forming a dielectric layer that applies a second stress to the semiconductor substrate, wherein at the selected location, a combined stress of the first stress and a second stress is substantially equal to the target stress; and

forming the dielectric layer on a backside of the semiconductor substrate using the material and the process conditions.

2. The method of claim 1, wherein the target stress is a substantially neutral stress.

3. The method of claim 1, wherein the forming the dielectric layer comprises:

forming a first sub-layer on the backside of the semiconductor substrate;

removing the first sub-layer from directly over substantially all p-type metal-oxide-semiconductor (PMOS) devices or substantially all n-type metal-oxide-semiconductor (NMOS) devices that are in the wafer; and

forming a second sub-layer over remaining portions of the first sub-layer, wherein the first and the second sub-layers apply stresses that have opposite stress types to the semiconductor substrate.

4. The method of claim 3, wherein the first and the second sub-layers are formed of substantially a same material, and wherein process conditions for forming the first sub-layer are different from process conditions for forming the second sub-layer.

5. The method of claim 1, wherein the finding the first stress comprises a step selected from the group consisting essentially of:

measuring the first stress at the selected location of the semiconductor substrate; and

measuring the first stress from another sample wafer.

6. The method of claim 1, wherein the target stress is selected from the group consisting essentially of a compressive stress and a tensile stress.

7. The method of claim 1, wherein the dielectric layer comprises a nitride.

8. A method comprising:

forming a through-substrate via (TSV) extending from a front surface of a semiconductor substrate of a wafer into the semiconductor substrate, wherein the wafer comprises a transistor at the front surface of the semiconductor substrate, wherein the semiconductor substrate comprises a back surface opposite to the front surface, and wherein the TSV applies a first stress to a nearby region of the semiconductor substrate, with the nearby region being adjacent to the TSV;

performing a backside grinding on the back surface of the semiconductor substrate to expose the TSV;

forming a backside isolation layer over and contacting the back surface, wherein the TSV is exposed through the backside isolation layer;

forming a redistribution line on the backside of the semiconductor substrate, wherein the redistribution line is over the backside isolation layer; and

forming a passivation layer comprising;

a first portion over the redistribution line;

a second portion on sidewalls of the redistribution line; and

a third portion lower than the first portion and the second portion, wherein the passivation layer applies a second stress to the nearby region, with the second stress being of an opposite type than the first stress.

9. The method of claim 8, wherein in the nearby region, the first stress is substantially neutralized by the second stress.

10. The method of claim 8 further comprising:

after the TSV is formed, measuring the first stress; and

before the forming the passivation layer, selecting a material and process conditions for forming the passivation layer that applies the second stress to the nearby region.

11. The method of claim 10 further comprising:

forming a sample wafer identical to the wafer;

forming a sample TSV in the sample wafer; and

after the sample TSV is formed on the sample wafer, measuring the first stress, wherein the first stress is equal to a stress applied by the sample TSV to the sample wafer.

12. The method of claim 8, wherein the passivation layer comprises a nitride.

13. A method comprising:

forming a through-substrate via (TSV) extending from a front surface of a semiconductor substrate of a wafer into the semiconductor substrate, wherein the wafer comprises a transistor at the front surface of the semiconductor substrate, wherein the semiconductor substrate comprises a back surface opposite to the front surface, and wherein the TSV applies a first stress to a nearby region of the semiconductor substrate, with the nearby region being adjacent to the TSV;

performing a backside grinding on the back surface of the semiconductor substrate to expose the TSV;

forming a backside isolation layer over and contacting the back surface, wherein the TSV is exposed through the backside isolation layer;

forming a redistribution line on the backside of the semiconductor substrate, wherein the redistribution line is over the backside isolation layer; and

forming a passivation layer comprising;

a first portion over the redistribution line;

a second portion on sidewalls of the redistribution line; and

a third portion lower than the first portion and the second portion, wherein the passivation layer applies a second stress to the nearby region, with the second stress being of a same type as the first stress.

14. The method of claim 13 further comprising:

after the TSV is formed, measuring the first stress; and

before the forming the passivation layer, selecting a material and process conditions for forming the passivation layer that applies the second stress to the semiconductor substrate.

15. The method of claim 13 further comprising:

forming a sample wafer identical to the wafer;

forming a sample TSV in the sample wafer; and

after the sample TSV is formed on the sample wafer, measuring the first stress, wherein the first stress is equal to a stress applied by the sample TSV to the sample wafer.

16. The method of claim 13, wherein the step of forming the passivation layer comprises:

forming a first sub-layer;

removing the first sub-layer from directly over substantially all p-type metal-oxide-semiconductor (PMOS) devices or substantially all n-type metal-oxide-semiconductor (NMOS) devices that are in the wafer; and

forming a second sub-layer over remaining portions of the first sub-layer.

17. The method of claim 13, wherein the passivation layer comprises a nitride.