Semiconductor image sensor module and method of manufacturing the same

• US 8,946,610 B2
• Filed: 06/01/2006
• Issued: 02/03/2015
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Sony Group Corp.
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Iwabuchi, Shin, Motoyoshi, Makoto
• Primary Examiner(s): LEE, JOHN R
• Application Number:
  US11/915,958
• Publication Number:
  US 20100276572A1
• Time in Patent Office: 3,169 Days
• Field of Search: 250/208.1, 348/294, 348/300, 348/301, 348/302, 348/308, 438/66, 438/67, 438/73, 438/74, 438/107, 438/108, 438/109, 257/443, 257/444, 257/447, 257/734, 257/737, 257/738, 257/777, 257/778, 257/780, 257/E31.054, 257/E21.499, 257/258, 257/291
• US Class Current: 250/208.1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 29/788 : with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H04N 23/54 : Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention provides a CMOS type semiconductor image sensor module in which the aperture ratio of the pixel is improved and at the same time chip use efficiency is attempted to be improved and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same. The semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip including an image sensor in which a plurality of pixels, each constituted by a photoelectric conversion element and transistors, are arranged, and a second semiconductor chip including an A/D converter array. Preferably, a third semiconductor chip including a memory element array is further laminated. Also, a semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip provided with the aforesaid image sensor and a fourth semiconductor chip provided with an analog type nonvolatile memory array.

Claims

1. An image sensor comprising:

a first semiconductor chip including a plurality of pixels arranged in a first array, each of the pixels including a photoelectric conversion element, and

a second semiconductor chip including a plurality of analog/digital converters arranged in a second array; and

a third semiconductor chip including a memory element array provided with at least a decoder and a sense amplifier,

wherein the first, second, and third semiconductor chips are stacked and electrically connected to one another, and

at least two of the first, second, and third semiconductor chips are electrically connected through a penetration contact portion passing through at least one of the first, second, and third semiconductor chips.

2. The image sensor according to claim 1, wherein

the image sensor is a back-illuminated image sensor, a first surface of the first semiconductor chip being opposite from a second surface of the first semiconductor chip, and the second surface of the first semiconductor chip being on a light-incident side of the first semiconductor chip.

3. The image sensor according to claim 2, wherein

the first surface of the first semiconductor chip is coupled to a first surface of a second semiconductor chip by a plurality of electroconductive connection bodies.

4. The image sensor according to claim 1, wherein

the plurality of analog/digital converters are arranged in a two-dimensional array.

5. The image sensor according to claim 4, wherein

the array of the plurality of pixels is arranged into pixel array blocks, and

one of the plurality of analog/digital converters corresponds to each of the pixel array blocks.

6. The image sensor according to claim 2, wherein

the first semiconductor chip includes a transistor region formed toward the first surface of the first semiconductor chip and a photodiode region formed toward the second surface of the first semiconductor ship, the photodiode region including photodiodes corresponding to each of the plurality of pixels and the transistor region including transistors corresponding to each of the photodiodes.

7. The image sensor according to claim 3, wherein

the electroconductive connection bodies include first pads formed on the first surface of the first semiconductor chip, second pads formed on the first surface of the second semiconductor chip, each first pad corresponding positionally with one of the second pads, and a bump formed between each of the corresponding first pads and second pads.

8. The image sensor according to claim 3, wherein the first surface of the first semiconductor chip is laminated to the first surface of the second semiconductor chip.

9. The image sensor according to claim 3, wherein

the first surface of the first semiconductor chip is bonded to the first surface of the second semiconductor chip with an adhesive material.

10. The image sensor according to claim 1, wherein the first and second semiconductor chips are arranged close to the third semiconductor chip such that a plurality of photoelectric conversion elements and a plurality of memory elements share one analog/digital converter.

11. The image sensor according to claim 10, wherein each of the memory elements is a volatile memory.

12. The image sensor according to claim 10, wherein each of the memory elements is a floating gate nonvolatile memory.

13. The image sensor according to claim 10, wherein each of the memory elements is an MONOS nonvolatile memory.

14. The image sensor according to claim 10, wherein each of the memory elements is a multivalued nonvolatile memory.

15. The image sensor according to claim 1, wherein a memory bit for parity check is included in the memory element array.

16. The image sensor according to claim 1, wherein a spare bit for relieving a defect is included in the memory element array.

26. The image sensor according to claim 1, wherein the first and second chips are electrically connected through the penetration contact portion.

27. The image sensor according to claim 1, wherein the second and third chips are electrically connected through the penetration contact portion.

17. An image sensor comprising:

a first semiconductor chip including a plurality of pixels arranged in a first array, each of the pixels including a photoelectric conversion element,

a second semiconductor chip including an analog nonvolatile memory array including a plurality of analog nonvolatile memories, and

a third semiconductor chip including a plurality of analog/digital converters arranged in a second array,

wherein the first, second, and third semiconductor chips are stacked and electrically connected to one another,

wherein at least two of the first, second, and third semiconductor chips are electrically connected through a penetration contact portion passing through at least one of the first, second, and third semiconductor chips, and

wherein an amount of information corresponding to an amount of accumulated electric charge is stored by the analog nonvolatile memories.

28. The image sensor according to claim 17, wherein the first and second chips are electrically connected through the penetration contact portion.

29. The image sensor according to claim 17, wherein the second and third chips are electrically connected through the penetration contact portion.

18. A method of making an image sensor module, comprising the steps of:

forming a first semiconductor chip, the first semiconductor chip including a plurality of pixels arranged two-dimensionally in a first array, each of the pixels including a photoelectric conversion element;

forming a second semiconductor chip, the second semiconductor chips including a plurality of analog/digital converters arranged in a second array;

forming a third semiconductor chip, the third semiconductor chip including a memory element array provided with at least a decoder and a sense amplifier; and

stacking and electrically connecting the first, second, and third semiconductor chips to one Another,

wherein at least two of the first, second, and third semiconductor chips are electrically connected through a penetration contact portion passing through at least one of the first, second, and third semiconductor chips.

19. The method according to claim 18, wherein the step of stacking and electrically connecting the first, second, and third semiconductor chips to one another includes the step of laminating the first semiconductor chip to the second semiconductor chip.

20. The method according to claim 18, wherein the step of stacking and electrically connecting the first, second, and third semiconductor chips to one another includes bonding a first surface of the first semiconductor chip to a first surface of the second semiconductor chip.

21. The method according to claim 20, further comprising forming first pads on the first surface of the first semiconductor chip and forming second pads on the first surface of the second semiconductor chip, each first pad corresponding positionally with one of the second pads, and forming a bump between each of the corresponding first pads and second pads.

22. The method according to claim 18, wherein the plurality of analog/digital converters are arranged in a two-dimensional array.

23. The method according to claim 18, further comprising connecting each of the plurality of pixels with a corresponding one of the plurality of analog/digital converters by a through-hole that passes through a wafer.

24. The method of making an image sensor according to claim 23, further comprising the step of:

laminating the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip and connecting the pixels of the image sensor with the memory through the analog/digital converters by means of through-holes which pass through the wafer vertically with respect to the wafer face.

30. The method of making an image sensor according to claim 18, wherein the first and second chips are electrically connected through the penetration contact portion.

31. The method of making an image sensor according to claim 18, wherein the second and third chips are electrically connected through the penetration contact portion.

25. A method of making an image sensor, comprising the steps of:

forming a first semiconductor chip, the first semiconductor chip including a plurality of pixels arranged in a first array, each of the pixels including a photoelectric conversion element;

forming a second semiconductor chip, the second semiconductor chip including an analog nonvolatile memory array including a plurality of analog nonvolatile memories provided with an analog nonvolatile memory array composed of a plurality of analog nonvolatile memories;

forming a third semiconductor chip, the third semiconductor chip including a plurality of analog/digital converters arranged in a second array;

stacking and electrically connecting the first, second, and third semiconductor chips to one another; and

connecting each of the pixels to one of the analog nonvolatile memories,

wherein at least two of the first, second, and third semiconductor chips are electrically connected through a penetration contact portion passing through at least one of the first, second, and third semiconductor chips.

32. The method of making an image sensor according to claim 25, wherein the first and second chips are electrically connected through the penetration contact portion.

33. The method of making an image sensor according to claim 25, wherein the second and third chips are electrically connected through the penetration contact portion.