Semiconductor element and display device using the same

• US 8,946,718 B2
• Filed: 12/19/2013
• Issued: 02/03/2015
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Murakami, Satoshi, Hayakawa, Masahiko, Yamazaki, Shunpei
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US14/133,820
• Publication Number:
  US 20140138720A1
• Time in Patent Office: 411 Days
• Field of Search: 257/66, 257/67, 257/72
• US Class Current: 257/66
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/1341 Filling or closing of cells
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 2102/3026 : Top emission
• CPC Class Codes: H10K 2102/311 : Flexible OLED
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: Y10S 438/95 : Multilayer mask including nonradiation sensitive layer

Abstract

A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a semiconductor layer including a channel region over the gate electrode with the gate insulating film therebetween;

an electrode comprising metal over and in contact with the semiconductor layer;

an inorganic insulating film comprising silicon and nitrogen over and in contact with the electrode, the inorganic insulating film including a first opening to expose a first portion of a top surface of the electrode;

an organic resin film over and in contact with the inorganic insulating film, the organic resin film including a second opening to expose the first portion and a second portion of a top surface of the inorganic insulating film; and

a pixel electrode over the organic resin film and in contact with the first portion through the first opening and the second opening,

wherein the organic resin film has a curved inner wall surface at the second opening.

2. The semiconductor device according to claim 1, wherein the semiconductor layer comprises silicon.

3. The semiconductor device according to claim 1, wherein an entirety of the first opening is surrounded by the second opening.

4. The semiconductor device according to claim 1, wherein the curved inner wall surface includes a convex surface.

5. The semiconductor device according to claim 1, wherein a curvature radius of the curved inner wall surface is 3 μ

m to 30 μ

m.

6. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a semiconductor layer including a channel region over the gate electrode with the gate insulating film therebetween;

an electrode comprising metal over and in contact with the semiconductor layer;

a first inorganic insulating film comprising silicon and nitrogen over and in contact with the electrode, the first inorganic insulating film including a first opening to expose a first portion of a top surface of the electrode;

an organic resin film over and in contact with the first inorganic insulating film, the organic resin film including a second opening to expose the first portion and a second portion of a top surface of the first inorganic insulating film;

a second inorganic insulating film comprising silicon and nitrogen over and in contact with the organic resin film, the second inorganic insulating film including a third opening to expose the first portion; and

a pixel electrode over the second inorganic insulating film and in contact with the first portion through the first opening, the second opening and the third opening,

wherein the organic resin film has a curved inner wall surface in contact with the second inorganic insulating film at the second opening.

7. The semiconductor device according to claim 6, wherein the second inorganic insulating film is in contact with a side surface of the second opening.

8. The semiconductor device according to claim 6, wherein the semiconductor layer comprises silicon.

9. The semiconductor device according to claim 6, wherein an entirety of the first opening is surrounded by the second opening.

10. The semiconductor device according to claim 6, wherein the curved inner wall surface includes a convex surface.

11. The semiconductor device according to claim 6, wherein a curvature radius of the curved inner wall surface is 3 μ

m to 30 μ

m.

12. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a semiconductor layer including a channel region over the gate electrode with the gate insulating film therebetween;

an electrode comprising metal over and in contact with the semiconductor layer;

a first inorganic insulating film comprising silicon and nitrogen over and in contact with the electrode, the first inorganic insulating film including a first opening to expose a first portion of a top surface of the electrode;

an organic resin film over and in contact with the first inorganic insulating film, the organic resin film including a second opening to expose the first portion and a second portion of a top surface of the first inorganic insulating film;

a second inorganic insulating film comprising silicon and nitrogen over and in contact with the second portion and the organic resin film, the second inorganic insulating film including a third opening to expose the first portion; and

a pixel electrode over the second inorganic insulating film and in contact with the first portion through the first opening, the second opening and the third opening,

wherein the organic resin film has a curved inner wall surface in contact with the second inorganic insulating film at the second opening.

13. The semiconductor device according to claim 12, wherein the semiconductor layer comprises silicon.

14. The semiconductor device according to claim 12, wherein an entirety of the first opening is surrounded by the second opening.

15. The semiconductor device according to claim 12, wherein the curved inner wall surface includes a convex surface.

16. The semiconductor device according to claim 12, wherein a curvature radius of the curved inner wall surface is 3 μ

m to 30 μ

m.

17. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a semiconductor layer including a channel region over the gate electrode with the gate insulating film therebetween;

an electrode comprising metal over and in contact with the semiconductor layer;

a first inorganic insulating film comprising silicon and nitrogen over and in contact with the electrode, the first inorganic insulating film including a first opening to expose a first portion of a top surface of the electrode;

an organic resin film over and in contact with the first inorganic insulating film, the organic resin film including a second opening to expose the first portion and a second portion of a top surface of the first inorganic insulating film;

a second inorganic insulating film comprising silicon and nitrogen over and in contact with the organic resin film, the second inorganic insulating film including a third opening to expose the first portion; and

a pixel electrode over the second inorganic insulating film and in contact with the first portion through the first opening, the second opening and the third opening,

wherein the second opening is larger than the first opening, and

wherein the organic resin film has a curved inner wall surface in contact with the second inorganic insulating film at the second opening.

18. The semiconductor device according to claim 17, wherein the semiconductor layer comprises silicon.

19. The semiconductor device according to claim 17, wherein an entirety of the first opening is surrounded by the second opening.

20. The semiconductor device according to claim 17, wherein the curved inner wall surface includes a convex surface.

21. The semiconductor device according to claim 17, wherein a curvature radius of the curved inner wall surface is 3 μ

m to 30 μ

m.

22. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a semiconductor layer including a channel region over the gate electrode with the gate insulating film therebetween;

an electrode comprising metal over and in contact with the semiconductor layer;

a first inorganic insulating film comprising silicon and nitrogen over and in contact with the electrode, the first inorganic insulating film including a first opening to expose a first portion of a top surface of the electrode;

an organic resin film over and in contact with the first inorganic insulating film, the organic resin film including a second opening to expose the first portion and a second portion of a top surface of the first inorganic insulating film;

a second inorganic insulating film comprising silicon and nitrogen over and in contact with the second portion and the organic resin film, the second inorganic insulating film including a third opening to expose the first portion; and

a pixel electrode over the second inorganic insulating film and in contact with the first portion through the first opening, the second opening and the third opening,

wherein the second opening is larger than the first opening, and

wherein the organic resin film has a curved inner wall surface in contact with the second inorganic insulating film at the second opening.

23. The semiconductor device according to claim 22, wherein the semiconductor layer comprises silicon.

24. The semiconductor device according to claim 22, wherein an entirety of the first opening is surrounded by the second opening.

25. The semiconductor device according to claim 22, wherein the curved inner wall surface includes a convex surface.

26. The semiconductor device according to claim 22, wherein a curvature radius of the curved inner wall surface is 3 μ

m to 30 μ

m.