Semiconductor device, method of manufacturing the same, and electronic device including the semiconductor device

• US 8,946,789 B2
• Filed: 11/14/2011
• Issued: 02/03/2015
• Est. Priority Date: 03/04/2011
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-kook, Lee, Sang-yoon, Choi, Woong
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US13/295,620
• Publication Number:
  US 20120223288A1
• Time in Patent Office: 1,177 Days
• Field of Search: 257/288, 257/E29.245, 257/E29.264, 257/E29.275, 977/938
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/23 Schottky diodes
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: H10K 10/486 the channel region comprising two or more active layers, e.g. forming pn heterojunctions
• CPC Class Codes: H10K 30/20 comprising organic-organic junctions, e.g. donor-acceptor junctions
• CPC Class Codes: H10K 30/50 Photovoltaic [PV] devices
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y02E 10/549 Organic PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

An example embodiment relates to a transistor including a channel layer. A channel layer of the transistor may include a plurality of unit layers spaced apart from each other in a vertical direction. Each of the unit layers may include a plurality of unit channels spaced apart from each other in a horizontal direction. The unit channels in each unit layer may form a stripe pattern. Each of the unit channels may include a plurality of nanostructures. Each nanostructure may have a nanotube or nanowire structure, for example a carbon nanotube (CNT).

Claims

1. A transistor comprising:

a channel layer,

the channel layer including a plurality of unit layers spaced apart from each other in a vertical direction, and

each of the plurality of unit layers including a plurality of unit channels spaced apart from each other in a horizontal direction, each of the plurality of unit channels including a plurality of nanostructures, the plurality of nanostructures in each of the plurality of unit channels including a network structure, the plurality of unit channels in each of the plurality of unit layers forming a stripe pattern;

a source arranged laterally on one side of the channel layer;

a drain arranged laterally on an other side of the channel layer; and

a gate corresponding to the channel layer; and

an insulation layer between every two adjacent unit layers, the insulation layer including a first insulation single layer between first and second unit layers of the plurality of unit layers, the first and second unit layers directly contacting lower and upper surfaces of the first insulation single layer, respectively.

2. The transistor of claim 1,

each of the plurality of nanostructures include one of a nanotube and a nanowire.

3. The transistor of claim 2, wherein

the plurality of nanostructures include carbon nanotubes (CNTs).

4. The transistor of claim 1, wherein

a ratio (L/W) of a length (L) to a width (W) of each of the plurality of unit channels is equal to or more than about 5.

5. The transistor of claim 1, wherein

the gate is a first gate,

the transistor further includes a second gate spaced apart from the first gate, and

the channel layer is disposed between the first and second gates.

6. An electronic device comprising the transistor of claim 1.

7. The electronic device of claim 6, wherein

the electronic device is a display.

8. The transistor of claim 1, wherein

the first and second unit layers have a same width as the first insulation single layer.