Memory cell with decoupled channels

• US 8,946,806 B2
• Filed: 07/24/2011
• Issued: 02/03/2015
• Est. Priority Date: 07/24/2011
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Tan, Shyue Seng, Toh, Eng Huat, Quek, Elgin, Tang, Yanzhe
• Primary Examiner(s): Lam, Cathy N
• Application Number:
  US13/189,554
• Publication Number:
  US 20130020626A1
• Time in Patent Office: 1,290 Days
• Field of Search: 257/316, 257/E21.422, 257/E21.632, 257/319, 257/314, 257/315
• US Class Current: 257/316
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.

Claims

1. A device comprising:

a substrate prepared with a memory cell region, the memory cell region comprises a memory cell, wherein the memory cell includes

an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,

an erase gate being disposed over the common S/D region, and

a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.

2. The device of claim 1 wherein the memory cell region comprises the memory cell and a second memory cell, wherein the memory cells are coupled in series to form a memory cell pair.

3. The device of claim 2 wherein the memory cell corresponds to a first memory cell and the second memory cell comprises:

an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,

an erase gate being disposed over the common S/D region, and

a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel; and

wherein the memory cells of the memory cell pair are configured as mirror images of each other.

4. The device of claim 3 wherein the first storage S/D region of the first memory cell is common with the first storage S/D region of the second memory cell.

5. The device of claim 1 wherein the erase gate contacts the substrate and common S/D region and isolated from a storage and an access gate by gate sidewall dielectric layers.

6. The device of claim 1 wherein the storage transistor includes first and second storage gate electrodes, wherein:

the first storage gate electrode is a floating gate and the second storage gate electrode is a control gate; and

the second storage gate is disposed above the first storage gate.

7. The device of claim 6 wherein the program gate is separated from the first storage S/D region by a program gate dielectric layer.

8. The device of claim 7 wherein the program channel is disposed from an edge of the program gate to the floating gate.

9. The device of claim 8 wherein the erase channel is disposed from an edge of the floating gate to the erase gate.

10. The device of claim 9 wherein the read channel is disposed below the floating gate.

11. The device of claim 6 wherein the floating gate is provided with a sharp floating gate tip disposed on a side of the floating gate adjacent to the erase gate.

12. A device comprising:

a substrate prepared with a memory cell region, the memory cell region comprises at least one memory cell, wherein the at least one memory cell includes

an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,

an erase gate being disposed over the common S/D region, and

a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.

13. The device of claim 12 wherein the storage transistor includes first and second storage gate electrodes, wherein:

the first storage gate electrode is a floating gate and the second storage gate electrode is a control gate; and

the second storage gate is disposed above the first storage gate.

14. The device of claim 13 wherein the floating gate is provided with a sharp floating gate tip disposed on a side of the floating gate adjacent to the erase gate.

15. A device comprising:

a substrate with a memory cell region having at least one memory cell, wherein the at least one memory cell comprises

an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,

an erase gate being disposed over the common S/D region, wherein the erase gate is isolated from a storage and an access gate by gate sidewall dielectric layers, and

a program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.

16. The device of claim 15 wherein the at least one memory cell comprises first and second memory cells, and wherein the first and second memory cells are coupled in series to form a memory cell pair.

17. The device of claim 16 wherein the first storage S/D region of the first memory cell is common with the first storage S/D region of the second memory cell.

18. The device of claim 15 wherein the storage transistor comprises a second storage gate electrode disposed above a first storage gate electrode.

19. The device of claim 18 wherein the storage transistor comprises an intergate dielectric layer which separates the first and second storage gate electrodes.

20. The device of claim 15 wherein:

the storage transistor comprises first and second gate electrodes; and

the first gate electrode comprises a sharp electrode tip disposed on a side of the first gate electrode layer adjacent to the erase gate.

21. The device of claim 15 wherein the program gate is separated from the first storage S/D region by a program gate dielectric layer.