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Memory cell with decoupled channels

  • US 8,946,806 B2
  • Filed: 07/24/2011
  • Issued: 02/03/2015
  • Est. Priority Date: 07/24/2011
  • Status: Active Grant
First Claim
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1. A device comprising:

  • a substrate prepared with a memory cell region, the memory cell region comprises a memory cell, wherein the memory cell includesan access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,an erase gate being disposed over the common S/D region, anda program gate being disposed over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel.

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