Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates

• US 8,946,814 B2
• Filed: 04/05/2013
• Issued: 02/03/2015
• Est. Priority Date: 04/05/2012
• Status: Active Grant

• Current Assignee: IceMOS Technology Ltd
• Original Assignee: IceMOS Technology Ltd
• Inventors: Anderson, Samuel, Ishiguro, Takeshi
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US13/857,715
• Publication Number:
  US 20130299900A1
• Time in Patent Office: 669 Days
• Field of Search: 257/288, 257/330, 257/491, 257/496, 257/E29.257, 438/197, 438/270, 438/271, 438/272
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7308 Schottky transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.

Claims

1. A superjunction semiconductor device comprising:

(a) a column of a first conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface to a first depth position, and having a first concentration of a dopant of the first conductivity type;

(b) a column of a second conductivity type opposite to the first conductivity type, having a second concentration of a dopant of the second conductivity type, and having a first sidewall surface proximate the column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface;

(c) a body contact region proximate the column of the second conductivity type, and having a third concentration of a dopant of the second conductivity type higher than the second concentration;

(d) a source electrode connected to the body contact region at a body contact interface including at least a first side of the body contact region other than a portion of the first main surface;

(e) a source region proximate the body contact region and the first main surface, the source region having a fourth concentration of a dopant of the first conductivity type higher than the first concentration, and connected to the source electrode at a source contact interface including at least a first side of the source region other than a portion of the first main surface; and

(f) a trench gate electrode disposed in a gate opening extending from the first main surface toward the second main surface to a depth position shallower than the first depth position, the trench gate electrode having a width defined in a direction parallel to the first main surface of the semiconductor layer, the gate opening having one or more sidewall surfaces proximate the source region and a body region, and having a bottom proximate the column of the first conductivity type, and a dielectric layer interposed between the trench gate electrode and the one or more sidewall surfaces of the gate opening and between the trench gate electrode and the bottom of the gate opening;

the dielectric layer having a thickness between the trench gate electrode and a bottom surface of the gate opening greater than or equal to the width of the trench gate electrode.

2. The superjunction semiconductor device of claim 1, wherein a bottom surface of the trench gate electrode is tapered in a direction toward the bottom of the gate opening.

3. The superjunction semiconductor device of claim 1, wherein the bottom of the gate opening is concave.

4. The superjunction semiconductor device of claim 2, wherein the bottom of the trench gate electrode is one of arcuate or chamfered.

5. The superjunction semiconductor device of claim 1, wherein the source contact interface further comprises at least a portion of a second side of the source region at the first main surface.

6. The superjunction semiconductor device of claim 1, wherein the first side of the source region and the first side of the body contact region are at least one of aligned with the second sidewall surface of the column of the second conductivity type and perpendicular to the second main surface.

7. The superjunction semiconductor device of claim 1, further comprising a body region proximate the column of the second conductivity type, the body contact region, and the source region, the body region having a fifth concentration of a dopant of the second conductivity type higher than the second concentration, but lower than the third concentration.

8. The superjunction semiconductor device of claim 1, further comprising a trench proximate at least one of the columns, the trench being filled with at least one of a semi-insulating material and an insulating material.

9. The superjunction semiconductor device of claim 1, wherein the column of the first conductivity type and the column of the second conductivity type comprise epitaxial layers.

10. The superjunction semiconductor device of claim 1, the device being selected from the group consisting of a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET), a superjunction metal-semiconductor field-effect transistor (MESFET), a superjunction Schottky transistor, a superjunction insulated-gate bipolar transistor (IGBT), a thyristor, and a superjunction diode.