High frequency switching MOSFETs with low output capacitance using a depletable P-shield

• US 8,946,816 B2
• Filed: 05/05/2014
• Issued: 02/03/2015
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Yilmaz, Hamza, Lui, Sik, Ng, Daniel
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US14/270,228
• Publication Number:
  US 20140239382A1
• Time in Patent Office: 274 Days
• Field of Search: 257/334, 257/E29.26, 257/E29.263, 438/270, 438/272
• US Class Current: 257/334
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A MOSFET device, comprising:

a semiconductor substrate of a first conductivity type wherein the substrate includes a lightly doped epitaxial region in a top portion of the substrate;

a body region of a second conductivity type formed in a top portion of the semiconductor substrate, wherein the second conductivity type is opposite the first conductivity type;

a plurality of active device structures formed from the semiconductor substrate and body region, wherein each active device structure comprises a gate electrode formed in a trench and insulated with a gate oxide, wherein an upper portion of the gate oxide is a thickness T₁ and a bottom portion of the gate oxide is a thickness T₂, wherein T₂ is greater than T₁;

a depletable shield of the second conductivity type formed in the semiconductor substrate at a depth at least partially below a bottom surface of one or more trenches, wherein the depletable shield is electrically connected to the body region;

an insulative gate cap formed over each gate electrode, wherein an insulating spacer is formed on the sidewalls of the gate cap and a conductive or semiconductor spacer is formed on the exposed side walls of the insulating spacer, an insulative layer over a top surface of the body region;

a conductive source metal layer formed over the insulative layer;

one or more electrical connections that connect the source metal layer with one or more source regions, wherein the one or more electrical connections are spaced apart from the gate cap by the insulative spacers.

2. The device of claim 1, wherein one or more of the depletable shields extend through the substrate to a drain contact of the first conductivity type formed in a bottom portion of the substrate.

3. The device of claim 1, wherein one or more of the depletable shields are formed completely below the bottom surface of the trenches.

4. The device of claim 1, wherein the connection between the depletable shield and the body layer is made in a primary plane of the device.

5. The device of claim 1, wherein the connection between the depletable shield and the body layer is made in a secondary plane of the device, wherein the secondary plane of the device is orthogonal to the primary plane of the device.

6. The device of claim 5, wherein a portion of the depletable shield is disconnected from the body layer, wherein a disconnected potion of the depletable shield is spaced apart from a connected portion of the depletable shield by a portion of the substrate configured to connect an epitaxial region of the first conductivity type formed proximate to the trenches to a drain contact of the first conductivity type formed in a bottom portion of the substrate.

7. The device of claim 6, wherein the disconnected portion of the depletable shield continuously extends below two or more trenches in the primary plane and is configured to form an orthogonal super-junction structure with the portion of the substrate configured to connect the epitaxial region to the drain contact.

8. The MOSFET device of claim 1, wherein the conductive or semiconductor spacer is a polysilicon spacer.

9. The MOSFET device of claim 8, wherein the polysilicon spacer is doped with dopants of the first conductivity type.

10. The MOSFET device of claim 9, further comprising:

a plurality of source regions of the first conductivity type formed in a top portion of the semiconductor substrate proximate to the plurality of trenches.

11. The MOSFET device of claim 1, further comprising one or more electrostatic discharge (ESD) protection features.

12. The MOSFET device of claim 1, further comprising one or more gate pickup trenches.

13. The MOSFET device of claim 1, further comprising a Schottky contact.

14. The MOSFET device of claim 13, wherein the Schottky contact further comprises a body clamp structure.