Electrostatic discharge protection element and electrostatic discharge protection chip and method of producing the same

• US 8,946,823 B2
• Filed: 09/06/2013
• Issued: 02/03/2015
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Klein, Wolfgang, Taddiken, Hans, Bakalski, Winfried
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ahmed, Shahed
• Application Number:
  US14/020,510
• Publication Number:
  US 20140001491A1
• Time in Patent Office: 515 Days
• Field of Search: 257/77, 257/E27.009, 257/355, 257/656, 257/544, 438/627
• US Class Current: 257/355
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8618 Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Claims

1. An electrostatic discharge (ESD) protection device comprising:

a first diode comprising a first doped region of a first doping type, a first barrier region of a second doping type, an intrinsic or a substantially low doping of the first or the second doping type, a second barrier region of the first doping type, and a second doped region of the second doping type, wherein the first doped region is coupled to a node to be protected, and wherein the second doped region is coupled to a discharge node of the ESD protection device; and

a second diode comprising a further first doped region of the first doping type, a further first barrier region of the second doping type, a further intrinsic or a substantially low doping of the first or the second doping type, a further second barrier region of the first doping type, and a further second doped region of the second doping type, wherein the further second doped region is coupled to the node to be protected, and wherein the further first doped region is coupled to the discharge node of the ESD protection device.

2. The ESD protection device of claim 1, wherein the first diode and the second diode are disposed in a high band gap material region of a substrate, wherein the high band gap material region comprises a material having a band gap higher than silicon.

3. The ESD protection device of claim 2, wherein the high band gap material region comprises GaN.

4. The ESD protection device of claim 2, wherein the high band gap material region comprises SiC, GaAs.

5. The ESD protection device of claim 1, wherein the first diode and the second diode are laterally disposed next to each other within a substrate.

6. The ESD protection device of claim 1, wherein the first diode and the second diode are vertical diodes, each having a cathode terminal and an anode terminal at opposite sides of a substrate.

7. An electrostatic discharge (ESD) protection device comprising:

a first doped region of a first doping type disposed in a substrate, the first doped region coupled to a node to be protected by the ESD protection device;

a first barrier region of a second doping type disposed under the first doped region;

a first semiconductor region disposed under the first barrier region;

a second barrier region of the first doping type contacting the first semiconductor region and disposed in the substrate;

a second doped region of the second doping type disposed in the substrate, wherein the second barrier region is disposed between the first semiconductor region and the second doped region, wherein the first doped region, the first barrier region, the first semiconductor region, the second barrier region, and the second doped region form a first diode;

a third doped region of the second doping type disposed in the substrate, the third doped region coupled to the node to be protected by the ESD protection device;

a third barrier region of the first doping type disposed under the third doped region;

a second semiconductor region disposed under the third barrier region;

a fourth barrier region of the second doping type contacting the second semiconductor region and disposed in the substrate; and

a fourth doped region of the first doping type disposed in the substrate, wherein the fourth barrier region is disposed between the second semiconductor region and the fourth doped region, wherein the third doped region, the third barrier region, the second semiconductor region, the fourth barrier region, and the fourth doped region form a second diode.

8. The ESD protection device of claim 7, wherein the first doped region, the first barrier region, the first semiconductor region, second barrier region, and the second doped region are disposed in a high band gap material region of the substrate, wherein the high band gap material region comprises a material having a band gap higher than silicon.

9. The ESD protection device of claim 8, wherein the high band gap material region comprises GaN.

10. The ESD protection device of claim 8, wherein the high band gap material region comprises SiC, GaAs.

11. The ESD protection device of claim 7, wherein the first semiconductor region and the second semiconductor region are part of a lightly doped epitaxial layer of the substrate.

12. The ESD protection device of claim 7, wherein the first diode and the second diode are connected in anti-parallel.

13. The ESD protection device of claim 7, further comprising a back side contact layer disposed on a back side of the substrate, the back side of the substrate being opposite a front side near the first doped region, wherein the back side contact layer is disposed under the second doped region and is coupled to a discharge node of the ESD protection device.

14. The ESD protection device of claim 7, wherein the first doped region and the second doped region are disposed laterally next to each other at a front side of the substrate.

15. The ESD protection device of claim 7, wherein the first semiconductor region is a epitaxial layer of the substrate, wherein the epitaxial layer is disposed over a substrate layer of the substrate, wherein the epitaxial layer comprises a lower doping than the substrate layer.

16. The ESD protection device of claim 15, further comprising an additional barrier layer disposed between the epitaxial layer and the substrate layer.