Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications

• US 8,946,829 B2
• Filed: 10/14/2011
• Issued: 02/03/2015
• Est. Priority Date: 10/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wann, Clement Hsingjen, Yeh, Ling-Yen, Shih, Chi-Yuan, Lin, Yi-Tang, Chang, Chih-Sheng, Liu, Chi-Wen
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US13/273,527
• Publication Number:
  US 20130093026A1
• Time in Patent Office: 1,208 Days
• Field of Search: 257/288, 257/400, 257/401, 257/E27.06, 257/E29.255, 257/E21.545
• US Class Current: 257/401
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

Claims

1. A fin field-effect transistor (FinFET) comprising:

a semiconductor substrate;

a plurality of fins on the substrate including one or more regular fins and one or more shaped fins, wherein regular fins and shaped fins have different top portion shapes;

an oxide layer on the semiconductor substrate embedding a bottom portion of the plurality of fins, wherein the embedded bottom portion of each fin of the plurality of fins has substantially the same shape; and

a gate structure over the one or more shaped fins.

2. The transistor of claim 1, wherein the one or more shaped fins include at least one shaped fin of a first shape and at least one shaped fin of a second shape.

3. The transistor of claim 1, wherein the one or more shaped fins is smaller than the one or more regular fins.

4. The transistor of claim 1, wherein the one or more shaped fins is larger than the one or more regular fins.

5. The transistor of claim 1, wherein the one or more shaped fins are each adjacent to only the one or more regular fins such that the spacing between adjacent fins in the transistor is uniform.

6. The transistor of claim 1, wherein the plurality of fins and the semiconductor substrate are a same material.

7. A fin field-effect transistor (FinFET) comprising:

a substrate;

an oxide layer on the substrate;

a first fin on the substrate, the first fin having a bottom portion embedded in the oxide layer, and a top portion above the oxide layer, wherein the top portion of the first fin has a first shape;

a second fin on the substrate, the second fin having a bottom portion embedded in the oxide layer, and a top portion above the oxide layer, wherein the top portion of the second fin has a second shape different from the first shape; and

a gate structure over the second fin.

8. The FinFET of claim 7, wherein the top portion of the second fin has a rounded top surface.

9. The FinFET of claim 7, further comprising a third fin on the substrate, the third fin having a bottom portion embedded in the oxide layer, and a top portion above the oxide layer, wherein the top portion of the third fin has the first shape, wherein the second fin is positioned between the first fin and the third fin.

10. The FinFET of claim 7, wherein the top portion of the second fin has sidewalls formed at an angle with respect to a top surface of the substrate.

11. The FinFET of claim 7, further comprising a third fin on the substrate, the third fin having a bottom portion embedded in the oxide layer, and a top portion above the oxide layer, wherein the top portion of the third fin has the second shape.

12. The FinFET of claim 7, wherein the second shape has a smaller dimension than the first shape in a direction parallel to a top surface of the substrate or in a direction perpendicular to the top surface of the substrate.