Non-volatile latch structures with small area for FPGA

• US 8,947,122 B2
• Filed: 03/14/2013
• Issued: 02/03/2015
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Prabhakar, Venkatraman
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/827,607
• Publication Number:
  US 20140197864A1
• Time in Patent Office: 691 Days
• Field of Search: None
• US Class Current: 326/46
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence

Abstract

A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit.

Claims

1. A latch circuit comprising:

a first non-volatile tri-gate device coupled between a source of supply voltage and an output node; and

a second non-volatile tri-gate device including a first end and a second end, wherein the first end is coupled to the first non-volatile tri-gate at the output node and the second end is coupled to ground.

2. The latch circuit of claim 1 wherein the first non-volatile tri-gate device comprises a first Metal-Oxide-Semiconductor (MOS) transistor, a second MOS transistor and a third transistor including a charge-trapping nitride layer.

3. The latch circuit of claim 2 wherein the third transistor is coupled between the first and second MOS transistors, and wherein each transistor shares a common current path.

4. The latch circuit of claim 1 wherein the second non-volatile tri-gate device comprises a first MOS transistor, a second MOS transistor and a third transistor including a charge-trapping nitride layer.

5. The latch circuit of claim 1 wherein the first tri-gate device comprises two control gates and a programming gate.

6. The latch circuit of claim 4 wherein the third transistor is coupled between the first and second MOS transistors, and wherein each transistor shares a common current path.

7. The latch circuit of claim 1 wherein the second tri-gate device comprises two control gates and a programming gate.

8. A latch circuit comprising:

a first non-volatile tri-gate device coupled between a first node and a bit line;

a second non-volatile tri-gate device coupled between a second node and a source line; and

a cross-coupled circuit coupled to a source of supply voltage, wherein the cross-coupled circuit is further coupled to the first non-volatile tri-gate at the first node and to the second non-volatile tri-gate at the second node.

9. The latch circuit of claim 8 wherein the first non-volatile tri-gate device comprises a first MOS transistor, a second MOS transistor and a third transistor including a charge-trapping nitride layer.

10. The latch circuit of claim 9 wherein the third transistor is coupled between the first and second MOS transistors, and wherein each transistor shares a common current path.

11. The latch circuit of claim 8 wherein the second non-volatile tri-gate device comprises a first MOS transistor, a second MOS transistor and a third transistor including a charge-trapping nitride layer.

12. The latch circuit of claim 11 wherein the third transistor is coupled between the first and second MOS transistors, and wherein each transistor shares a common current path.

13. The latch circuit of claim 8 wherein a first gate of the first tri-gate device and a first gate of the second tri-gate device are coupled together to a first control node.

14. The latch circuit of claim 13 wherein a second gate of the first tri-gate device and a second gate of the second tri-gate device are coupled together to a programming node.

15. The latch circuit of claim 14 wherein a third gate of the first tri-gate device and a third gate of the second tri-gate device are coupled together to a second control node.

16. The latch circuit of claim 8 wherein the cross-coupled circuit comprises a first and a second cross-coupled MOS transistors.

17. The latch circuit of claim 8 further comprising a buffer circuit coupled between the second node and an output node.

18. A method of operating a non-volatile latch circuit, the method comprising:

providing a first tri-gate non-volatile device;

providing a second tri-gate non-volatile device;

coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, wherein the coupling of the first and second tri-gate non-volatile devices is disposed within the non-volatile latch circuit;

erasing the first tri-gate non-volatile device;

programming the second tri-gate non-volatile device; and

latching an output node of the latch circuit to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices.

19. The method of claim 18 wherein the coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device comprises direct coupling.

20. The method of claim 18 wherein the coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device comprises indirect coupling through a cross-coupled circuit.