Voltage multiplier charge pump buck

• US 8,947,157 B2
• Filed: 02/07/2013
• Issued: 02/03/2015
• Est. Priority Date: 04/20/2010
• Status: Expired due to Fees

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Levesque, Chris, Zimlich, David, Berchtold, Jean-Christophe
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US13/761,500
• Publication Number:
  US 20130147445A1
• Time in Patent Office: 726 Days
• Field of Search: 327535-538, 327/540, 327/541, 327/543, 363/59, 363/60, 323/265, 323/266, 323/271
• US Class Current: 327/536
• CPC Class Codes: G05F 1/595 semiconductor devices connected in series
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/171 A filter circuit coupled to the output of an amplifier
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/414 A switch being coupled in the output circuit of an amplifier to switch the output on/off
• CPC Class Codes: H03F 2200/417 A switch coupled in the output circuit of an amplifier being controlled by a circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/504 the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21157 : A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/602 : Combinations of several amplifiers
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

DC to DC converter circuitry includes a dual phase charge pump and at least one pair of multiplier phase circuits. The dual phase charge pump is coupled to each one of the at least one pair of multiplier circuits and adapted to receive a DC input voltage and only four control signals, and produce a stepped-up output voltage. Each one of the at least one pair of multiplier phase circuits are adapted to receive the stepped-up output voltage, a cross-coupled control signal from the other multiplier phase circuit in the pair of multiplier phase circuits, and a different one of the control signals and further multiply the stepped-up output voltage to produce a multiplied stepped-up output voltage with a magnitude that is approximately three times that of the DC input voltage or greater.

Claims

1. Direct current (DC) to DC converter circuitry comprising:

a dual phase charge pump adapted to receive a DC input voltage and only four control signals and produce a stepped-up output voltage, wherein the magnitude of the stepped-up output voltage is based at least in part on the four control signals; and

at least one pair of multiplier phase circuits coupled to the dual phase charge pump, wherein each one of the at least one pair of multiplier phase circuits is adapted to receive the stepped-up output voltage, a cross-coupled control signal from the other multiplier phase circuit in the pair of multiplier phase circuits, and a different one of the four control signals and further multiply the stepped-up output voltage to produce a multiplied stepped-up output voltage.

2. The DC to DC converter circuitry of claim 1 wherein the magnitude of the multiplied stepped-up output voltage is approximately three times that of the DC input voltage or greater.

3. The DC to DC converter circuitry of claim 1 further comprising buck output circuitry coupled to the at least one pair of multiplier phase circuits.

4. The DC to DC converter circuitry of claim 3 wherein the buck output circuitry comprises:

a buck regulating switch coupled between ground an input node;

a buck regulating capacitor coupled between ground and an output node; and

a buck regulating inductor including a first terminal coupled to the input node and a second terminal coupled to the output node.

5. The DC to DC converter circuitry of claim 4 wherein the buck output circuitry is adapted to regulate the multiplied stepped-up output voltage in order to produce a regulated multiplied stepped-up output voltage.

6. The DC to DC converter circuitry of claim 5 wherein the buck regulating switch is adapted to selectively couple the first terminal of the buck regulating inductor between ground and the input terminal.

7. The DC to DC converter circuitry of claim 1 wherein the at least one pair of multiplier phase circuits includes:

a first multiplier phase circuit including a first multiplying flying capacitor and a first multiplying switching network adapted to selectively couple the first multiplying flying capacitor between an input node and ground during a charging phase of operation, and the dual phase charge pump and an output node during a pumping phase of operation; and

a second multiplier phase including a second multiplying flying capacitor and a second multiplying switching network adapted to selectively couple the second multiplying flying capacitor between the input node and ground during a charging phase of operation, and the dual phase charge pump and the output node during a pumping phase of operation.

8. The DC to DC converter circuitry of claim 7 wherein:

the first multiplying flying capacitor includes a negative terminal that is selectively coupled between a first output node of the dual phase charge pump and ground based upon one of the four control signals and a positive terminal that is selectively coupled between the input node and the output node based upon the cross-coupled control signal delivered from the second multiplier phase; and

the second multiplying flying capacitor includes a negative terminal that is selectively coupled between a second output node of the dual phase charge pump and ground based upon one of the four control signals and a positive terminal that is selectively coupled between the input node and the output node based upon the cross-coupled control signal delivered from the first multiplier phase.

9. The DC to DC converter circuitry of claim 7 wherein the cross-coupled control signal from the second multiplier phase is delivered from the positive terminal of the second multiplying flying capacitor, and the cross-coupled control signal from the first multiplier phase is delivered from the positive terminal of the first multiplying flying capacitor.

10. The DC to DC converter circuitry of claim 9 wherein the dual phase charge pump comprises:

a first flying capacitor;

a first charge pump switching network adapted to selectively couple the first flying capacitor between the input node and ground during a charging phase of operation, and the input node and the first charge pump output node during a pumping phase of operation;

a second flying capacitor; and

a second charge pump switching network adapted to selectively couple the second flying capacitor between the input node and ground during a charging phase of operation, and the input node and the second charge pump output node during a pumping phase of operation.

11. The DC to DC converter circuitry of claim 10 wherein:

the first flying capacitor includes a negative terminal that is selectively coupled between the input node and ground based upon a first control signal and a second control signal and a positive terminal that is selectively coupled between the input node and the first charge pump output node based upon a first cross-coupled control signal delivered from the second flying capacitor; and

the second flying capacitor includes a negative terminal that is selectively coupled between the input node and ground based upon a third control signal and a fourth control signal and a positive terminal that is selectively coupled between the input node and the second charge pump output node based upon a second cross-coupled control signal delivered from the first flying capacitor.

12. The DC to DC converter circuitry of claim 11 wherein the first cross-coupled control signal is delivered from the positive terminal of the second flying capacitor, and the second cross-coupled control signal is delivered from the positive terminal of the first flying capacitor.

13. The DC to DC converter circuitry of claim 10 wherein the first multiplying switching network, the second multiplying switching network, the first charge pump switching network, and the second charge pump switching network comprise a plurality of complementary metal oxide semiconductor (CMOS) switches.

14. The DC to DC converter circuitry of claim 13 wherein the first multiplying switching network comprises:

a first switch adapted to selectively couple the positive terminal of the first multiplying flying capacitor to the input node;

a second switch adapted to selectively couple the positive terminal of the first multiplying flying capacitor to a first output node; and

a third switch adapted to selectively couple the negative terminal of the first multiplying flying capacitor to ground.

15. The DC to DC converter circuitry of claim 14 wherein the second switch of the first multiplying switching network includes a drain contact, a gate contact, a source contact, and a body contact, and further wherein the body contact of the second switch is coupled to a CMOS well.

16. The DC to DC converter circuitry of claim 13 wherein the second multiplying switching network comprises:

a first switch adapted to selectively couple the positive terminal of the second multiplying flying capacitor to the input node;

a second switch adapted to selectively couple the positive terminal of the second multiplying flying capacitor to the second output node; and

a third switch adapted to selectively couple the negative terminal of the second multiplying flying capacitor to ground.

17. The DC to DC converter of claim 16 wherein the second switch of the second multiplying switching network includes a drain contact, a gate contact, a source contact, and a body contact, and further wherein the body contact of the second switch is coupled to a CMOS well.

18. The DC to DC converter circuitry of claim 13 wherein the first charge pump switching network comprises:

a first switch adapted to couple the positive terminal of the first flying capacitor to the input node;

a second switch adapted to selectively couple the positive terminal of the first flying capacitor to the first charge pump output node;

a third switch adapted to selectively couple the negative terminal of the first flying capacitor to the input node; and

a fourth switch adapted to selectively couple the negative terminal of the first flying capacitor to ground.

19. The DC to DC converter circuitry of claim 18 wherein the second switch of the first charge pump switching network includes a drain contact, a gate contact, a source contact, and a body contact, and further wherein the body contact of the second switch is coupled to a CMOS well.

20. The DC to DC converter circuitry of claim 13 wherein the second charge pump switching network comprises:

a first switch adapted to selectively couple the positive terminal of the second flying capacitor to the input node;

a second switch adapted to selectively couple the positive terminal of the second flying capacitor to the second charge pump output node;

a third switch adapted to selectively couple the negative terminal of the second flying capacitor to the input node; and

a fourth switch adapted to selectively couple the negative terminal of the second flying capacitor to ground.

21. The DC to DC converter circuitry of claim 20 wherein the second switch of the second charge pump switching network includes a drain contact, a gate contact, a source contact, and a body contact, and further wherein the body contact of the second switch is coupled to a CMOS well.