Display panel

• US 8,947,409 B2
• Filed: 09/01/2010
• Issued: 02/03/2015
• Est. Priority Date: 12/14/2009
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Koo, Bon-Yong
• Primary Examiner(s): Johnson, Gerald
• Application Number:
  US12/873,923
• Publication Number:
  US 20110141074A1
• Time in Patent Office: 1,616 Days
• Field of Search: 345/205
• US Class Current: 345/205
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A display panel has an amorphous silicon gate driver. A variable capacitor is formed at one end of a gate line to prevent the deterioration of display quality due to high temperature noise. A predetermined level of capacitance is provided to the variable capacitor to the reduce ripple of gate voltage and eliminate the high temperature noise.

Claims

1. A display panel, comprising:

a display area that includes a gate line, the gate line having electrical characteristics comprising a gate line resistance and a gate line capacitance;

a main gate driver that is connected to one end of the gate line, that applies a gate on voltage to the gate line, and is integrated on a substrate; and

a sub gate driver that is connected to an other end of the gate line and includes at least one variable capacitor,

wherein an end of the variable capacitor is connected to the other end of the gate line such that the variable capacitor is in parallel with the capacitance of an adjacent gate line.

2. The display panel of claim 1 wherein an other end of the variable capacitor receives voltage from the outside.

3. The display panel of claim 2, wherein the variable capacitor has a capacitance that varies according to the voltage applied to the other end of the variable capacitor.

4. The display panel of claim 3, wherein the display panel includes more than two variable capacitors connected in parallel.

5. The display panel of claim 3, wherein:

the display area further comprises a data line that intersects the gate line,

one electrode of the variable capacitor is made of the same material as the gate line,

the other electrode of the variable capacitor is made of the same material as the data line, and

a gate insulating layer covers the gate line and is between the one electrode of the variable capacitor and the other electrode of the variable capacitor.

6. The display panel of claim 5, wherein the sub gate driver further comprises a gate voltage discharge transistor that discharges the voltage applied to the gate line.

7. The display panel of claim 6, wherein the gate voltage discharge transistor comprises:

a control electrode that is connected to a gate line of a next stage,

an input electrode that is connected to a gate line of a current stage, and

an output electrode that is connected to low voltage.

8. The display panel of claim 7, wherein the main gate driver includes a thin film transistor including amorphous silicon.

9. The display panel of claim 8, wherein;

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-down driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting as transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and as gate off voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate on voltage output from the output unit to a gate off voltage.

10. The display panel of claim 1, wherein the variable capacitor has a capacitance that varies according to the voltage applied to the other end of the variable capacitor.

11. The display panel of claim 10, wherein the display panel includes more than two variable capacitors connected in parallel.

12. The display panel of claim 10, wherein:

the display area further comprises a data line that intersects the gate line,

one electrode of the variable capacitor is made of the same material as the gate line,

the other electrode of the variable capacitor is made of the same material as the data line, and

a gate insulating layer covers the gate line and is between the one electrode of the variable capacitor and the other electrode of the variable capacitor.

13. The display panel of claim 12, wherein the sub gate driver further comprises a gate voltage discharge transistor that discharges voltage applied to the gate line.

14. The display panel of claim 13, wherein the gate voltage discharge transistor has a control electrode that is connected to a gate line of the next stage, an input electrode that is connected to a gate line of a current stage, and an output electrode that is connected to low voltage.

15. The display panel of claim 14, wherein the main gate driver includes a thin film transistor comprising amorphous.

16. The display panel of claim 15, wherein:

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-down driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting a transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and a gate off voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate an voltage output from the output unit to a gate off voltage.

17. The display panel of claim 1, wherein the display panel includes more than two variable capacitors connected in parallel.

18. The display panel of claim 1, wherein:

the display area further comprises a data line that intersects the gate line,

one electrode of the variable capacitor is made of the same material as the gate line,

the other electrode of the variable capacitor is made of the same material as the data line, and a gate insulating layer that covers the gate line and is between the one electrode of the variable capacitor and the other electrode of the variable capacitor.

19. The display panel of claim 18, wherein the sub gate driver further comprises a gate voltage discharge transistor that discharges voltage applied to the gate line.

20. The display panel of claim 19, wherein the gate voltage discharge transistor comprises:

a control electrode that is connected to a gate line of a next stage,

an input electrode that is connected to a gate line of a current stage, and

an output electrode that is connected to low voltage.

21. The display panel of claim 20, wherein the main gate driver includes a thin film transistor comprising amorphous silicon.

22. The display panel of claim 21, wherein:

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-do driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting a transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and a gate off voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate on voltage output from the output unit to a gate of voltage.

23. The display panel of claim 1, wherein the sub gate driver includes a gate voltage discharge transistor that discharges the voltage applied to the gate line.

24. The display panel of claim 23, wherein the gate voltage discharge transistor has a control electrode that is connected to a gate line of the next stage, an input electrode that is connected to a gate line of a current stage, and an output electrode that is connected to low voltage.

25. The display panel of claim 24, wherein the main gate driver includes a thin film transistor comprising amorphous silicon.

26. The display panel of claim 25, wherein:

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-down driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting a transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and a gate off voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate on voltage output from the output unit to a gate off voltage.

27. The display panel of claim 1, wherein the main gate driver includes a thin film transistor comprising amorphous silicon.

28. The display panel of claim 27, wherein:

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-down driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting a transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and a gate of voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate on voltage output from the output unit to a gate off voltage.

29. The display panel of claim 1, wherein:

the main gate driver includes an input unit, a pull-up driver, a transmit signal generator, an output unit, and a pull-down driver;

the input unit is responsive to an input voltage and has an output connected to the transfer signal generator, to the pull-down driver and to the output unit;

the pull-up driver is responsive to clock signals and has an output connected to the pull-down driver;

the transfer signal generator is responsive to the clock signals and has an output connected to a next stage for outputting a transfer signal to the next stage;

the output unit is connected to the gate line for providing a gate on voltage and a gate ofr voltage to the gate line; and

the pull-down driver is responsive to a gate voltage of the next stage for changing a gate on voltage output from the output unit to a gate off voltage.