Memory controller with circuitry to set memory device-specific reference voltages

• US 8,948,212 B2
• Filed: 01/13/2014
• Issued: 02/03/2015
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared LeVan, Donnelly, Kevin S., Sidiropoulos, Stefanos, Stark, Donald C., Horowitz, Mark A., Yu, Leung, Vu, Roxanne, Kim, Jun, Garlepp, Bruno W., Ho, Tsyr-Chyang, Lau, Benedict Chung-Kwong
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US14/154,068
• Publication Number:
  US 20140229667A1
• Time in Patent Office: 386 Days
• Field of Search: 370/516, 711/105
• US Class Current: 370/516
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Claims

1. A memory controller, comprising:

an interface circuit for coupling the memory controller to one or more memory devices via a bus;

control logic, coupled to the interface circuit, the control logic comprising circuitry

to address an individual memory device of the one or more memory devices; and

to set a memory device-specific value in a reference voltage register in the individual memory device; and

the interface circuit to transmit a data signal to the individual memory device;

wherein the memory device-specific value stored in the reference voltage register of the individual memory device controls a reference voltage used by the individual memory device when receiving the data signal transmitted by the memory controller to the individual memory device.

2. The memory controller of claim 1, wherein the memory controller is configured to convey, via the interface, a device identifier identifying the individual memory device and an opcode identifying an operation to be performed by the individual memory device.

3. The memory controller of claim 1, wherein the control logic is to set the memory device-specific value in the reference voltage register in the individual memory device in accordance with a slave-specific voltage calibration of the value in the reference voltage register directed by the memory controller.

4. The memory controller of claim 3, wherein, in conjunction with the slave-specific voltage calibration, the memory controller is configured to initiate a calibration mode in the individual memory device.

5. The memory controller of claim 3, wherein the memory controller is configured to use a scanning window approach during said slave-specific voltage calibration of the value in the reference voltage register.

6. The memory controller of claim 3, wherein the control logic is further to transmit data to the individual memory device during the slave-specific voltage calibration of the value in the reference voltage register in the individual memory device.

7. The memory controller of claim 1, wherein the control logic is configured to set the value in the reference voltage register in the individual memory device in accordance with an offset value located between offset values corresponding to high and low pass/fail transition points.

8. The memory controller of claim 1, wherein the control logic is further to set a memory device-specific read output drive value, distinct from the memory device-specific value stored in the reference voltage register, in a circuit of the individual memory device distinct from the reference voltage register.

9. The memory controller of claim 8, wherein the circuit distinct from the reference voltage register is coupled to a transmitter of the individual memory device.

10. The memory controller of claim 8, wherein the circuit distinct from the reference voltage register is a current control circuit and the transmitter is a controlled current source output driver of the individual memory device.

11. The memory controller of claim 8, wherein the control logic is further to send an up/down signal to the individual memory device to increment or decrement the memory device-specific read output drive value.

12. A method of slave-specific calibration, performed by a memory controller coupled by a bus to one or more memory devices, the method comprising:

addressing an individual memory device of the one or more memory devices;

setting a memory device-specific value in a reference voltage register in the individual memory device; and

transmitting a data signal to the individual memory device;

wherein the memory device-specific value stored in the reference voltage register of the individual memory device controls a reference voltage used by the individual memory device when receiving the data signal transmitted by the memory controller to the individual memory device.

13. The method of claim 12, further comprising conveying via the bus a device identifier identifying the individual memory device and an opcode identifying an operation to be performed by the individual memory device.

14. The method of claim 12, including setting the memory device-specific value in the reference voltage register in the individual memory device in accordance with a slave-specific voltage calibration of the value in the reference voltage register directed by the memory controller.

15. The method of claim 14, further comprising, in conjunction with the slave-specific voltage calibration, initiating a calibration mode in the individual memory device.

16. The method of claim 14, further comprising using a scanning window approach during said slave-specific voltage calibration.

17. The method of claim 14, including transmitting data to the individual memory device during the slave-specific voltage calibration of the value in the reference voltage register in the individual memory device.

18. The method of claim 12, including setting the value in the reference voltage register in the individual memory device in accordance with an offset value located between the offset values corresponding to high and low pass/fail transition points.

19. The method of claim 12, further comprising setting a memory device-specific read output drive value, distinct from the memory device-specific value stored in the reference voltage register, in a circuit of the individual memory device distinct from the reference voltage register.

20. The method of claim 19, including sending an up/down signal to the individual memory device to increment or decrement the memory device-specific read output drive value.