Inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer

• US 8,948,495 B2
• Filed: 03/02/2013
• Issued: 02/03/2015
• Est. Priority Date: 08/01/2012
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Marcuccilli, Gino, Widmann, Amir, Chang, Ellis, Robinson, John, Park, Allen
• Primary Examiner(s): Cunningham, Gregory F
• Application Number:
  US13/783,291
• Publication Number:
  US 20140037187A1
• Time in Patent Office: 703 Days
• Field of Search: 257/620, 257/E21.023, 257/E21.03, 257/E21.24, 257/E21.524, 257/E23.179, 382/149, 378/34
• US Class Current: 382/149
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.

Claims

1. A method for inspecting a wafer, comprising:

acquiring images for multiple die printed on a wafer, wherein each of the multiple die is printed by performing a double patterning lithography process on the wafer, and wherein the multiple die comprise two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay;

comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and

detecting defects in the multiple die printed at the modulated values based on results of said comparing, wherein said acquiring, said comparing, and said detecting are performed using a computer system.

2. The method of claim 1, further comprising acquiring images for multiple die printed on another wafer, wherein each of the multiple die on the other wafer is printed by performing the double patterning lithography process on the other wafer, and wherein the multiple die on the other wafer comprise two or more die printed at nominal values of focus and exposure for the double patterning lithography process and one or more die printed at modulated values of the focus and exposure;

comparing images acquired for the multiple die printed at the nominal values of the focus and exposure to images acquired for the multiple die printed at the modulated values of the focus and exposure; and

detecting defects in the multiple die printed at the modulated values of the focus and exposure based on results of said comparing.

3. The method of claim 2, further comprising comparing the defects detected at substantially the same within die position in the multiple die printed at the modulated values of the focus and exposure and, based on results of said comparing the defects and the modulated values of the focus and exposure corresponding to the defects, determining points in a design for the multiple die that are most susceptible to defects due to modulation of the focus and exposure.

4. The method of claim 2, further comprising comparing portions of design data proximate positions of the defects, detected in the multiple die printed at the modulated values of the focus and exposure, in design data space, determining if the design data in the portions is at least similar based on results of said comparing the portions, binning the defects, detected in the multiple die printed at the modulated values of the focus and exposure, in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar, and determining which of the defects, detected in the multiple die printed at the modulated values of the focus and exposure, are systematic defects based on results of the binning.

5. The method of claim 2, further comprising identifying problems in patterned features being printed in the multiple die based on the defects detected in the multiple die printed at the modulated values of the focus and exposure.

6. The method of claim 2, further comprising identifying problems in a design for the multiple die based on the defects detected in the multiple die printed at the modulated values of the focus and exposure.

7. The method of claim 1, further comprising determining a process window for the double patterning lithography process based on the defects.

8. The method of claim 1, wherein the defects comprise systematic defects caused by modulation of values of the overlay.

9. The method of claim 1, further comprising comparing portions of design data proximate positions of the defects in design data space, determining if the design data in the portions is at least similar based on results of said comparing the portions, binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar, and determining which of the defects are systematic defects based on results of the binning.

10. The method of claim 9, further comprising generating a pareto chart illustrating the number of defects binned into two or more of the groups.

11. The method of claim 1, further comprising comparing the defects detected at substantially the same within die position in the multiple die printed at the modulated values of the overlay and, based on results of said comparing the defects and the modulated values of the overlay corresponding to the defects, determining points in a design for the multiple die that are most susceptible to defects due to modulation of the overlay.

12. The method of claim 11, further comprising determining an impact of the modulation of the overlay on the points in the design that are most susceptible to the defects.

13. The method of claim 1, further comprising determining one or more characteristics of one or more reticles used in the double patterning lithography process based on the defects.

14. The method of claim 1, further comprising altering one or more parameters of the double patterning lithography process based on the defects.

15. The method of claim 1, further comprising altering one or more parameters of a control process used for the double patterning lithography process based on the defects.

16. The method of claim 1, further comprising altering one or more parameters of a design for the multiple die based on the defects.

17. The method of claim 1, further comprising comparing two or more of the images acquired for the multiple die printed at the nominal values to each other and detecting defects in the multiple die printed at the nominal values based on results of said comparing the two or more images acquired for the multiple die printed at the nominal values to each other.

18. The method of claim 1, further comprising performing metrology on one or more of the multiple die, determining overlay errors, focus errors, dose errors, or some combination thereof of the double patterning lithography process based on results of the metrology, and simulating one or more characteristics of a device being formed from the one or more multiple die by applying the overlay errors, focus errors, dose errors, or some combination thereof to design data for the one or more multiple die.

19. The method of claim 1, wherein said acquiring comprises acquiring the images for the two or more die printed at the nominal values by simulating how the two or more die would be printed on the wafer at the nominal values.

20. The method of claim 1, wherein the images for the two or more die printed at the nominal values comprise simulated images acquired from a computer-readable storage medium.

29. The method of claim 1, further comprising determining one or more parameters of a metrology process to be performed on the wafer or other wafers on which the lithography process is performed based on the one or more characteristics of the device.

36. The method of claim 1, wherein the lithography process is a double patterning lithography process, wherein said performing the metrology is performed after a first patterning step of the lithography process, and wherein the method further comprises determining one or more parameters of a second patterning step of the lithography process based on the overlay errors, focus errors, dose errors, or some combination thereof.

21. A method for predicting one or more characteristics of a device being formed on a wafer, comprising:

performing metrology on one or more die formed on a wafer using a lithography process;

determining overlay errors, focus errors, dose errors, or some combination thereof of the lithography process in the one or more die based on results of the metrology; and

simulating one or more characteristics of a device being formed from the one or more die by applying the overlay errors, focus errors, dose errors, or some combination thereof to design data for the one or more die, wherein said determining and said simulating are performed using a computer system.

22. The method of claim 21, further comprising determining a sensitivity of the one or more characteristics of the device to the overlay errors, focus errors, dose errors, or some combination thereof.

23. The method of claim 21, further comprising determining one or more positions of one or more metrology targets to be formed on other wafers using the lithography process based on sensitivity of the one or more characteristics of the device to the overlay errors, focus errors, dose errors, or some combination thereof.

24. The method of claim 21, further comprising dispositioning the wafer based on the one or more characteristics of the device.

25. The method of claim 21, wherein said simulating comprises re-sizing individual polygons in the design data based on the overlay errors, focus errors, dose errors, or some combination thereof to determine areas in the design data that may have one or more failure mechanisms due to the overlay errors, focus errors, dose errors, or some combination thereof.

26. The method of claim 21, further comprising predicting yield of a fabrication process that includes the lithography process based on the one or more characteristics of the device, wherein predicting the yield is performed in-line.

27. The method of claim 21, further comprising determining a sampling scheme for the wafer based on the one or more characteristics of the device, wherein determining the sampling scheme is performed in-line.

28. The method of claim 21, further comprising determining one or more parameters of an inspection process to be performed on the wafer or other wafers on which the lithography process is performed based on the one or more characteristics of the device.

30. The method of claim 21, wherein said simulating comprises simulating the one or more characteristics of the device by determining overlay correctables, focus correctables, dose correctables, or some combination thereof from the overlay errors, focus errors, dose errors, or some combination thereof, respectively, and applying the overlay correctables, focus correctables, dose correctables, or some combination thereof to the design data for the one or more die.

31. The method of claim 21, further comprising determining a process window for the design data based on the one or more characteristics and the overlay errors, focus errors, dose errors, or some combination thereof.

32. The method of claim 21, further comprising determining a rework strategy for the wafer or other wafers on which the lithography process is performed based on the one or more characteristics and the overlay errors, focus errors, dose errors, or some combination thereof.

33. The method of claim 21, further comprising determining one or more areas in the design data at which the overlay errors, focus errors, dose errors, or some combination thereof are more critical for the one or more characteristics of the device.

34. The method of claim 21, further comprising applying a local model of overlay, dose, and focus to at least one of the one or more areas.

35. The method of claim 34, further comprising comparing results of said applying the local model to results of applying a global model of overlay, dose, and focus to the design data to determine an accuracy of the global model.

37. The method of claim 21, wherein the lithography process is a double patterning lithography process, wherein the one or more die comprise two or more die printed at nominal values of overlay and one or more die printed at modulated values of the overlay, and wherein the method further comprises acquiring images of at least one of the two or more die printed at the nominal values of the overlay and at least one of the one or more die printed at the modulated values of the overlay, comparing the images acquired for the at least one of the two or more die printed at the nominal values of the overlay to the images acquired for the at least one of the one or more die printed at the modulated values of the overlay, and detecting defects in the one or more die printed at the modulated values based on results of said comparing.