Partitioned radio-frequency apparatus and associated methods

• US 8,948,708 B2
• Filed: 05/21/2014
• Issued: 02/03/2015
• Est. Priority Date: 01/12/2001
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Kerth, Donald A., Behrens, Richard T., Scott, Jeffrey W., Vishakhadatta, G. Diwakar, Tuttle, G. Tyson, Srinivasan, Vishnu
• Primary Examiner(s): Lee, John J
• Application Number:
  US14/284,310
• Publication Number:
  US 20140256279A1
• Time in Patent Office: 258 Days
• Field of Search: 455/78, 455/75, 455/74, 455/88, 455/83, 455/553.1, 455/313, 455/333, 455/190.1, 455/189.1
• US Class Current: 455/73
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Claims

1. An apparatus comprising:

a radio-frequency (RF) receiver, comprising;

first down-converter circuitry coupled to receive an RF signal and to generate first in-phase and first quadrature signals;

analog-to-digital converter (ADC) circuitry coupled to receive the first in-phase and first quadrature signals and to generate second in-phase and second quadrature signals;

second down-converter circuitry coupled to receive the second in-phase and second quadrature signals and to generate third in-phase and third quadrature signals; and

finite impulse-response (FIR) filter circuitry coupled to receive the third in-phase and third quadrature signals and to generate fourth in-phase and fourth quadrature signals, wherein the FIR filter has programmable response characteristics.

2. The apparatus according to claim 1, wherein the RF receiver satisfies requirements of a plurality of standards that govern RF receiver performance.

3. The apparatus according to claim 1, wherein the RF receiver can receive a plurality of types of RF signals.

4. The apparatus according to claim 1, wherein the FIR filter circuitry comprises channel-select filter circuitry.

5. The apparatus according to claim 1, further comprising digital-to-analog converter (DAC) circuitry coupled to receive the fourth in-phase and fourth quadrature signals and to produce fifth in-phase and fifth quadrature signals.

6. The apparatus according to claim 5, further comprising low noise amplifier (LNA) circuitry coupled to receive and amplify the RF signal to generate an amplified RF signal, and to provide the amplified RF signal to the first down-converter circuitry.

7. The apparatus according to claim 6, further comprising a pair of analog programmable-gain amplifiers (PGAs) coupled between the first down-converter circuitry and the ADC circuitry, the pair of analog PGAs to receive and amplify the first in-phase and first quadrature signals to generate amplified first in-phase and first quadrature signals, and to provide the amplified first in-phase and first quadrature signals to the ADC circuitry.

8. The apparatus according to claim 5, further comprising a pair of digital programmable-gain amplifiers (PGAs) coupled between the FIR filter circuitry and the DAC circuitry, the pair of digital PGAs to receive and amplify the fourth in-phase and fourth quadrature signals to generate amplified fourth in-phase and fourth quadrature signals, and to provide the amplified fourth in-phase and fourth quadrature signals to the DAC circuitry.

9. The apparatus according to claim 1, further comprising local oscillator (LO) circuitry to provide an RF LO signal to the first down-converter circuitry.

10. The apparatus according to claim 1, wherein the ADC circuitry comprises sigma-delta ADC circuitry.

11. A radio-frequency (RF) receiver, comprising:

filter circuitry to receive an RF signal and to generate a filtered RF signal;

analog down-converter circuitry coupled to receive the filtered RF signal and to generate a first analog in-phase signal and a first analog quadrature signal;

analog-to-digital converter (ADC) circuitry coupled to receive the first analog in-phase signal and the first analog quadrature signal and to convert the first analog in-phase signal and the first analog quadrature signal to a first digital in-phase signal and a first digital quadrature signal;

digital down-converter circuitry coupled to receive the first digital in-phase signal and the first digital quadrature signal and to generate a second digital in-phase signal and a second digital quadrature signal;

finite impulse-response (FIR) filter circuitry having programmable response characteristics, the FIR filter circuitry coupled to receive the second digital in-phase signal and the second digital quadrature signal and to generate a third digital in-phase signal and a third digital quadrature signal; and

digital-to-analog (DAC) circuitry coupled to receive the third digital in-phase signal and the third digital quadrature signal and to convert the third digital in-phase signal and the third digital quadrature signal to a second analog in-phase signal and a second analog quadrature signal.

12. The RF receiver according to claim 11, wherein the RF receiver satisfies requirements of a plurality of standards that govern RF receiver performance.

13. The RF receiver according to claim 11, wherein the RF receiver can receive a plurality of types of RF signals.

14. The RF receiver according to claim 11, wherein the FIR filter circuitry comprises channel-select filter circuitry.

15. A method of processing a received radio-frequency (RF) signal, the method comprising:

down-converting the received RF signal to generate first in-phase and first quadrature signals;

converting the first in-phase and first quadrature signals to second in-phase and second quadrature signals by using analog-to-digital converter (ADC) circuitry;

down-converting the second in-phase and second quadrature signals to generate third in-phase and third quadrature signals; and

using finite impulse-response (FIR) filter circuitry having programmable response characteristics to filter the third in-phase and third quadrature signals to generate fourth in-phase and fourth quadrature signals.

16. The method according to claim 15, wherein the RF receiver satisfies requirements of a plurality of standards that govern RF receiver performance.

17. The method according to claim 15, wherein the RF receiver can receive a plurality of types of RF signals.

18. The method according to claim 15, wherein using the FIR filter circuitry further comprises using the programmable response characteristics of the FIR filter circuitry to select channels.

19. The method according to claim 15, further comprising amplifying, using low noise amplifier (LNA) circuitry, the received RF signal before down-converting the received RF signal.

20. The method according to claim 15, wherein down-converting the received RF signal further comprises using an RF local oscillator (LO) signal.