Computing floating-point polynomials in an integrated circuit device
First Claim
1. Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, said input variable represented by a mantissa and an exponent, said circuitry having a number of bits of precision and comprising:
- a plurality of coefficient memories, each respective one of said coefficient memories corresponding to a respective one of said terms of said polynomial, wherein;
for each respective one of said terms of said polynomial, said respective one of said coefficient memories that corresponds to said respective one of said terms of said polynomial is loaded with a plurality of instances of a respective coefficient for said respective one of said terms of said polynomial, andsaid instances of said respective coefficient for said respective one of said terms of said polynomial are multiple versions of said respective coefficient for said respective one of said terms of said polynomial, each version being shifted by a different number of bits; and
respective address circuitry associated with each respective one of said coefficient memories, said respective address circuitry selecting one of said instances of said respective coefficient for said respective one of said terms of said polynomial based on said exponent.
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Abstract
Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, where the input variable has a mantissa and an exponent, and the circuitry has a number of bits of precision, includes multiplier circuitry that calculates a common power of the input variable factored out of terms of the polynomial having powers of the variable greater than 1. The polynomial circuitry further includes, for each respective remaining term of the polynomial that contributes to the number of bits of precision: (1) a coefficient memory loaded with a plurality of instances of a coefficient for the respective term, each instance being shifted by a different number of bits, (2) address circuitry for selecting one of the instances of the coefficient based on the exponent, and (3) circuitry for combining the selected instance of the coefficient with a corresponding power of the input variable to compute the respective term.
410 Citations
26 Claims
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1. Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, said input variable represented by a mantissa and an exponent, said circuitry having a number of bits of precision and comprising:
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a plurality of coefficient memories, each respective one of said coefficient memories corresponding to a respective one of said terms of said polynomial, wherein; for each respective one of said terms of said polynomial, said respective one of said coefficient memories that corresponds to said respective one of said terms of said polynomial is loaded with a plurality of instances of a respective coefficient for said respective one of said terms of said polynomial, and said instances of said respective coefficient for said respective one of said terms of said polynomial are multiple versions of said respective coefficient for said respective one of said terms of said polynomial, each version being shifted by a different number of bits; and respective address circuitry associated with each respective one of said coefficient memories, said respective address circuitry selecting one of said instances of said respective coefficient for said respective one of said terms of said polynomial based on said exponent. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of configuring a programmable device as circuitry for calculating a polynomial having terms including powers of an input variable, said input variable represented by a mantissa and an exponent, said circuitry having a number of bits of precision, said method comprising:
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configuring, on said programmable device; a plurality of coefficient memories, each respective one of said coefficient memories corresponding to a respective one of said terms of said polynomial, wherein; for each respective one of said terms of said polynomial, said respective one of said coefficient memories that corresponds to said respective one of said terms of said polynomial is loaded with a plurality of instances of a respective coefficient for said respective one of said terms of said polynomial, and said instances of said respective coefficient corresponding to said respective one of said terms of said polynomial are multiple versions of said respective coefficient for said respective one of said terms of said polynomial, each version being shifted by a different number of bits; and respective address circuitry associated with each respective one of said coefficient memories, said respective address circuitry selecting one of said instances of said respective coefficient corresponding to said respective one of said terms of said polynomial based on said exponent. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A non-transitory machine-readable data storage medium encoded with non-transitory machine-executable instructions for configuring a programmable device as circuitry for calculating a polynomial having terms including powers of an input variable, said input variable represented by a mantissa and an exponent, said circuitry having a number of bits of precision, said instructions comprising:
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instructions to configure circuitry of said programmable device as; a plurality of coefficient memories, each respective one of said coefficient memories corresponding to a respective one of said terms of said polynomial, and being wherein; for each respective one of said terms of said polynomial, said respective one of said coefficient memories that corresponds to said respective one of said terms of said polynomial is loaded with a plurality of respective instances of a respective coefficient for said respective one of said terms of said polynomial, and said instances of said respective coefficient corresponding to said respective one of said terms of said polynomial are multiple versions of said coefficient for said respective one of said terms of said polynomial, each version being shifted by a different number of bits; and address circuitry for selecting one of said instances of said respective coefficient based on said exponent. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A method of using circuitry to calculate a polynomial having terms including powers of an input variable, said input variable represented by a mantissa and an exponent, said circuitry having a number of bits of precision, said method comprising:
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for each respective one of said terms of said polynomial, shifting, by a different number of bits, a plurality of instances of a respective coefficient corresponding to said respective one of said terms of said polynomial, for each respective one of said terms of said polynomial, loading a respective one of a plurality of coefficient memories with said plurality of instances of said respective coefficient corresponding to said respective one of said terms of said polynomial, and for each respective one of said terms of said polynomial, selecting one of said instances of said respective coefficient corresponding to said respective one of said terms of said polynomial by using said exponent as an address into said respective one of a plurality of coefficient memories. - View Dependent Claims (26)
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Specification