Automatic generation of cache-optimized code

• US 8,949,532 B1
• Filed: 03/31/2014
• Issued: 02/03/2015
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: The MathWorks, Inc.
• Original Assignee: The MathWorks, Inc.
• Inventors: Koh, David, Belge, Murat
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US14/230,277
• Time in Patent Office: 309 Days
• Field of Search: 711/118
• US Class Current: 711/118
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements

Abstract

A system receives cache conditions and software information related to a software application, and automatically generates an optimal cache management scheme for the software application based on the received cache conditions and software information.

Claims

1. A method comprising:

receiving information associated with an application,

the receiving being performed by a computing device;

receiving information associated with related sections of code of the application,

the receiving the information associated with the related sections of the code of the application being performed by the computing device;

aligning the related sections of the code of the application to one or more cache line boundaries,

the aligning the related sections of the code of the application to the one or more cache line boundaries reducing thrashing with respect to a quantity of thrashing occurring absent aligning the related sections of the code of the application to the one or more cache line boundaries, and

the aligning the related sections of the code of the application to the one or more cache line boundaries being performed by the computing device;

grouping, based on align the related sections of the code of the application to the one or more cache line boundaries, the related sections of the code of the application to create grouped sections of code,

the grouping being performed by the computing device;

distributing the grouped sections of code to a section of memory,

the distributing being performed by the computing device;

determining one or more particular sections of the grouped sections of code,

the determining being performed by the computing device; and

performing, based on a size of the section of the memory, an operation on the determined one or more particular sections of the grouped sections of code,

the performing being performed by the computing device.

2. The method of claim 1, where

the computing device includes a multi-core processor, and

each core shares a cache with each other core.

3. The method of claim 1, where

the computing device includes a multi-core processor,

each core include a respective cache, and

each core does not share the respective cache with each other core.

4. The method of claim 1, where

the computing device includes a multi-core processor,

each core include a respective cache,

each core does not share the respective cache with each other core, and

each core shares an additional cache with each other core,

the additional cache being different than each respective cache.

5. The method of claim 1, where, when performing the operation, the method includes:

locking the determined one or more particular sections of the grouped sections of code in a cache.

6. The method of claim 1, where

when aligning the related sections of the code of the application to the one or more cache line boundaries, the method includes:

aligning the related sections of the code of the application to the one or more cache line boundaries based on a cache management scheme to create aligned code, and

when grouping the related sections of the code of the application, the method includes;

grouping the aligned code.

7. The method of claim 1, where, when aligning the related sections of the code of the application to the one or more cache line boundaries, the method includes:

aligning the related sections of the code of the application to the one or more cache line boundaries based on one or more user-specified cache conditions.

8. A non-transitory computer-readable medium storing instructions, the instructions comprising:

one or more instructions which, when executed by a processor, cause the processor to;

receive information associated with an application;

receive information associated with related sections of code of the application;

align the related sections of code of the application to one or more cache line boundaries,

the aligning the related sections of the code of the application to the one or more cache line boundaries reducing thrashing with respect to a quantity of thrashing occurring absent aligning the related sections of the code of the application to the one or more cache line boundaries;

group, based on aligning the related sections of the code of the application to the one or more cache line boundaries, the related sections of the code of the application to create grouped sections of code;

distribute the grouped sections of code to a section of memory;

determine one or more particular sections of the grouped sections of code; and

perform, based on a size of the section of the memory, an operation on the determined one or more particular sections of the grouped sections of code.

9. The non-transitory computer-readable medium of claim 8, where

the processor is a multi-core processor, and

each core shares a cache with each other core.

10. The non-transitory computer-readable medium of claim 8, where

the processor is a multi-core processor,

each core include a respective cache, and

each core does not share the respective cache with each other core.

11. The non-transitory computer-readable medium of claim 8, where

the processor is a multi-core processor,

each core include a respective cache,

each core does not share the respective cache with each other core, and

each core shares an additional cache with each other core,

the additional cache being different than each respective cache.

12. The non-transitory computer-readable medium of claim 8, where the one or more instructions to perform the operation include:

one or more instructions to lock the determined one or more particular sections of the grouped sections of code in a cache.

13. The non-transitory computer-readable medium of claim 8, where

the one or more instructions to align the related sections of the code of the application to the one or more cache line boundaries further include:

one or more instructions to align the related sections of the code of the application to the one or more cache line boundaries based on a cache management scheme to create aligned code, and

the one or more instructions to group the related sections of the code of the application further include;

one or more instructions to group the aligned code.

14. The non-transitory computer-readable medium of claim 8, where the one or more instructions to align the related sections of the code of the application to the one or more cache line boundaries further include:

one or more instructions to align the related sections of the code of the application to the one or more cache line boundaries based on one or more user-specified cache conditions.

15. A device comprising:

a memory to store instructions; and

a processor to execute the instructions to;

receive information associated with an application;

receive information associated with related sections of code of the application;

align the related sections of code of the application to one or more cache line boundaries,

the aligning the related sections of the code of the application to the one or more cache line boundaries reducing thrashing with respect to a quantity of thrashing occurring absent aligning the related sections of the code of the application to the one or more cache line boundaries;

group, based on aligning the related sections of the code of the application to the one or more cache line boundaries, the related sections of the code of the application to create grouped sections of code;

distribute the grouped sections of code to a section of memory;

determine one or more particular sections of the grouped sections of code; and

perform, based on a size of the section of the memory, an operation on the determined one or more particular sections of the grouped sections of code.

16. The device of claim 15, where

the processor is a multi-core processor, and

each core shares a cache with each other core.

17. The device of claim 15, where

the processor is a multi-core processor,

each core include a respective cache, and

each core does not share the respective cache with each other core.

18. The device of claim 15, where

the processor is a multi-core processor,

each core include a respective cache,

each core does not share the respective cache with each other core, and

each core shares an additional cache with each other core,

the additional cache being different than each respective cache.

19. The device of claim 15, where

the processor, when aligning the related sections of the code of the application to the one or more cache line boundaries, is further to:

align the related sections of the code of the application to the one or more cache line boundaries based on a cache management scheme to create aligned code,

the processor, when performing the operation, is further to;

lock the determined one or more particular sections of the grouped sections of code in a cache, and

the processor, when grouping the related sections of the code of the application, is further to;

group the aligned code.

20. The device of claim 15, where the processor, when aligning the related sections of the code of the application to the one or more cache line boundaries, is further to:

align the related sections of the code of the application to the one or more cache line boundaries based on one or more user-specified cache conditions.