Power on reset circuit
First Claim
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1. A power on reset circuit, comprising:
- a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror to supply a first current to a first line and a second current to a second line;
a comparative voltage generator to generate a comparative voltage using the first current provided via the first line;
a driver connected to the second line, the driver to activate a reset signal in response to a voltage of the second line; and
a ground selecting transistor to connect the second line and a ground node according to the comparative voltage, wherein the comparative voltage generator includes;
a first impedance element connected to the first line and a second impedance element connected between the first impedance element and the ground node, wherein a node voltage of a node between the first and second impedance elements is provided as the comparative voltage, anda detection transistor having a gate connected with the node formed between the first and second impedance elements, a first end of the detection transistor connected with a first node formed between the first line and the first impedance element and a second end of the detection transistor connected with the ground node.
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Abstract
Embodiments may disclose a power on reset circuit, which includes: a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror being configured to supply a first current to a first line and a second current to a second line; a comparative voltage generator configured to generate a comparative voltage using the first current provided via the first line; a driver connected to the second line, the driver being configured to activate a reset signal in response to a voltage of the second line; and a ground selecting transistor configured to connect the second line and a ground node according to the comparative voltage.
8 Citations
16 Claims
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1. A power on reset circuit, comprising:
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a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror to supply a first current to a first line and a second current to a second line; a comparative voltage generator to generate a comparative voltage using the first current provided via the first line; a driver connected to the second line, the driver to activate a reset signal in response to a voltage of the second line; and a ground selecting transistor to connect the second line and a ground node according to the comparative voltage, wherein the comparative voltage generator includes; a first impedance element connected to the first line and a second impedance element connected between the first impedance element and the ground node, wherein a node voltage of a node between the first and second impedance elements is provided as the comparative voltage, and a detection transistor having a gate connected with the node formed between the first and second impedance elements, a first end of the detection transistor connected with a first node formed between the first line and the first impedance element and a second end of the detection transistor connected with the ground node. - View Dependent Claims (2, 3, 4, 5)
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6. A power on reset circuit, comprising:
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a voltage level detecting part to receive a power supply voltage, the voltage level detecting part including a detection node having a voltage varied according to the power supply voltage; and a driver to output a reset signal when the voltage of the detection node is higher than a predetermined voltage, wherein the voltage level detecting part includes; a comparative voltage generator to generate a comparative voltage varied according to the power supply voltage; and a ground selecting transistor to connect the detection node and a ground node according to the comparative voltage, wherein the voltage level detecting part includes a current mirror which includes; a first transistor having a first end connected to receive the power supply voltage; a second transistor having a first end connected to receive the power supply voltage; and a control impedance element connected to a second end of the first transistor and the comparative voltage generator, wherein gates of the first and second transistors are connected to each other, the gate of the first transistor connected with the second end of the first transistor and a second end of the second transistor connected with the detection node. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A computing system, comprising:
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a memory; a user interface; a central processing unit; a power on reset circuit providing a reset signal for controlling a reset operation of the memory, the power on reset circuit including; a voltage level detecting part to receive a power supply voltage, the voltage level detecting part including a detection node having a voltage varied according to the power supply voltage; and a driver being to output the reset signal when the voltage of the detection node is higher than a predetermined voltage, the voltage level detecting part including; a comparative voltage generator to generate a comparative voltage varied according to the power supply voltage; and a ground selecting transistor being configured to connect the detection node and a ground node according to the comparative voltage; and a bus which is electrically connected to the memory, the user interface, the central processing unit, and the power on reset circuit, wherein the current mirror includes; a first transistor having a first end connected to receive the power supply voltage; a second transistor having a first end connected to receive the power supply voltage; and a control impedance element connected to a second end of the first transistor and the comparative voltage generator, wherein gates of the first and second transistors are connected to each other, the gate of the first transistor connected with the second end of the first transistor, and a second end of the second transistor connected with the detection node. - View Dependent Claims (14, 15, 16)
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Specification