Segmented data storage

• US 8,949,684 B1
• Filed: 09/01/2009
• Issued: 02/03/2015
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shalvi, Ofir, Rotbard, Barak, Golov, Oren, Anholt, Micha, Perlmutter, Uri
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US12/551,583
• Time in Patent Office: 1,981 Days
• Field of Search: None
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

A method for data storage includes assigning in a memory that includes one or more storage devices a first storage area for storage of user data, and a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data. Input data is processed to produce redundancy data, and the input data is stored in the first storage area using at least one first write command. The redundancy data is stored in the second storage area using at least one second write command, separate from the first write command.

Claims

1. A method for data storage, comprising:

estimating reliability of one or more multi-level memory cells in a memory, wherein the estimating the reliability includes determining a number of program and erase cycles that have been performed on the one or more multi-level memory cells;

partitioning the memory into a first storage area and a second storage area dependent upon the estimated reliability;

processing input data to produce first redundancy data and second redundancy data, wherein the second redundancy data incudes a larger number of redundancy bits than the first redundancy data;

storing the input data and the first redundancy data in the first storage area, wherein storing the input data includes mapping bit values of the input data to programming levels in a binary order;

storing the second redundancy data in the second storage area; and

evaluating a criterion with respect to the stored input data, and, responsively to the criterion, selecting to perform one of;

reconstructing the input data irrespective of the second redundancy data stored in the second storage area by reading the input data from the first storage area; and

reading the second redundancy data from the second storage area and reconstructing the input data responsively to the second redundancy data;

wherein reconstructing the input data responsively to the second redundancy data comprises reusing readout data from a first page of the stored input data in a reading of a second page of the stored input data.

2. The method according to claim 1, wherein the criterion comprises a success of an attempt to reconstruct the input data by reading the input data and the first redundancy data from the first storage area irrespective of the second redundancy data stored in the second storage area.

3. The method according to claim 1, wherein processing the input data to produce the first redundancy data and the second redundancy data comprises encoding the input data using first and second Error Correction Codes (ECC) to produce respective first and second sets of parity bits, wherein storing the input data and the first redundancy data comprises storing the first set of the parity bits in the first storage area, and wherein storing the second redundancy data comprises storing the second set of the parity bits in the second storage area.

4. The method according to claim 3, wherein reconstructing the input data irrespective of the second redundancy data comprises reading the first set of the parity bits from the first storage area and decoding the first ECC, and wherein reconstructing the input data responsively to the second redundancy data comprises reading the second set of the parity bits from the second storage area and decoding the second ECC.

5. The method according to claim 1, wherein evaluating the criterion comprises assessing a time period that elapsed since the input data was stored.

6. The method according to claim 1, wherein evaluating the criterion comprises assessing a wear level of memory cells holding the input data.

7. The method according to claim 1, wherein reading the input data and the first redundancy data comprises accessing the first storage area, and wherein reading the second redundancy data comprises accessing the second storage area.

8. The method according to claim 1, wherein each multi-level memory cell is configured to store at least a first bit and a second bit, and wherein reading the first redundancy data comprises reading the first bit using one or more first read thresholds and reading the second bit using one or more second read thresholds, such that at least a common read threshold is common to the first and second read thresholds, and correcting at least one error in reading the second bit with respect to the common read threshold based on the read first bit.

9. The method according to claim 1, wherein storing the input data and the first redundancy data in the first storage area comprises programming at least one multi-level memory cell included in the first storage area dependent upon the input data and the first redundancy data using a first storage configuration;

and wherein storing the second redundancy data in the second storage area comprises programming at least one multi-level analog memory cell included in the second storage area dependent upon the second redundancy data using the first storage configuration; and

the method further comprising detecting that shut-off of electrical power to the memory is imminent, and re-programming the at least one multi-level memory cell included in the first storage area and the at least one multi-level memory cell included in the second storage area using a second storage configuration.

10. The method according to claim 1, wherein the memory includes at least first and second storage devices implemented using first and second different storage media types, wherein the first storage area is assigned in the first storage device, and wherein the second storage area is assigned in the second storage device.

11. An apparatus for data storage, comprising:

an interface, which is coupled to communicate with a memory; and

circuitry coupled to the memory, wherein the circuitry is configured to;

estimate reliability of one or more multi-level memory cells in the memory, wherein to estimate the reliability of the one or more multi-level memory cells in the memory, the circuitry is further configured to determine a number of program and erase cycles that have been performed on the one or more multi-level memory cells;

partitioning the memory into a first storage area and a second storage area dependent upon the estimated reliability;

process input data to produce first redundancy data and second redundancy data, wherein the second redundancy data includes a larger number of redundancy bits than the first redundancy data;

store the input data and the first redundancy data in the first storage area;

wherein to store the input data the circuitry is further configured to map bit values of the input data to programming levels in a binary order;

store the second redundancy data in the second storage area; and

evaluate a criterion with respect to the stored input data, and, responsively to the criterion, selecting to perform one of;

reconstruct the input data irrespective of the second redundancy data stored in the second storage area by reading the input data from the first storage area; and

read the second redundancy data from the second storage area and reconstructing the input data responsively to the second redundancy data;

wherein to reconstruct the input data responsively to the read second redundancy data the circuitry is further configured to reuse readout data from a first page of the stored input data in a reading of a second page of the stored input data.

12. The apparatus according to claim 11, wherein the criterion comprises a success of an attempt to reconstruct the input data by reading the input data and the first redundancy data from the first storage area irrespective of the second redundancy data stored in the second storage area.

13. The apparatus according to claim 11, wherein to process the input data to produce the first redundancy data and the second redundancy data, the circuitry is further configured to encode the input data using first and second Error Correction Codes (ECC) to produce respective first and second sets of parity bits, and to store the first set of the parity bits in the first storage area and to store the second set of the parity bits in the second storage area.

14. The apparatus according to claim 13, wherein the circuitry is further configured to reconstruct the input data irrespective of the second redundancy data by reading the first set of the parity bits from the first storage area and decoding the first ECC, and to reconstruct the input data responsively to the second redundancy data by reading the second set of the parity bits from the second storage area and decoding the second ECC.

15. The apparatus according to claim 11, wherein the circuitry is further configured to evaluate the criterion by assessing a time period that elapsed since the input data was stored.

16. The apparatus according to claim 11, wherein the circuitry is further configured to evaluate the criterion by assessing a wear level of the one or more multi-level memory cells holding the input data.

17. The apparatus according to claim 11, wherein to store the input data in the first storage area the circuitry is further configured to store the input data and the first redundancy data in the first storage area using at least one first write command, and wherein to store the second redundancy data in the second storage area the circuitry is further configured to store the second redundancy data in the second storage area using at least one second write command, different from the first write command.

18. The apparatus according to claim 11, wherein each multi-level memory cell is configured to store at least a first bit and a second bit, and wherein the circuitry is configured to read the first bit using one or more first read thresholds, to read the second bit using one or more second read thresholds such that at least a common read threshold is common to the first and second read thresholds, and to correct at least one error in reading the second bit with respect to the common read threshold based on the read first bit.

19. The apparatus according to claim 11, wherein to store the input data and the first redundancy data in the first storage area, the circuitry is further configured to program at least one multi-level memory cell included in the first storage area dependent on the input data and the first redundancy data using a first storage configuration;

and wherein to store the second redundancy data in the second storage area, the circuitry is further configured to program at least one multi-level memory included in the second storage area dependent upon the second redundancy data using the first storage configuration; and

wherein the circuitry is further configured to detect that shut-off of electrical power to the memory is imminent, and to re-program the at least one multi-level memory cell of the first storage area and the at least one multi-level memory cell of the second storage area using a second storage configuration responsive to the detection of the shut-off.

20. The apparatus according to claim 11, wherein the memory includes at least first and second storage devices implemented using first and second different storage media types, and wherein the circuitry is configured to assign the first storage area in the first storage device and to assign the second storage area in the second storage device.