System and method of emulating multiple custom prototype boards

• US 8,949,752 B2
• Filed: 11/25/2013
• Issued: 02/03/2015
• Est. Priority Date: 12/01/2012
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Wang, Ming-Yang, Shei, Sweyyan
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US14/089,522
• Publication Number:
  US 20140157215A1
• Time in Patent Office: 435 Days
• Field of Search: None
• US Class Current: 716/105
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.

Claims

1. A method for emulating a circuit design using a plurality of prototyping boards, the method comprising:

connecting a first prototyping board having a set of programmable logic components to a first interface having a set of programmable logic components using a first set of wires, the first prototyping board being described by a first plurality of board description files;

partitioning the circuit design according to the first plurality of board description files into the first prototyping board using the set of programmable logic components of the first prototyping board for emulating the circuit design;

configuring the set of programmable logic components of the first prototyping board with a module configured to transmit data between the first prototyping board and the first interface using at least one of the first set of wires; and

configuring the set of programmable logic components of the first interface with at least one of interface logic that provides communication with another interface or workstation connected to the first interface using a second set of wires or an interconnection fabric that provides communication between a plurality of prototyping boards.

2. The method of claim 1 wherein the module is configured to probe the emulation of the circuit design and communicate probe data to the first interface.

3. The method of claim 2 wherein the module is configure to communicate the probe data to the first interface using the at least one of the first set of wires and a serial protocol.

4. The method of claim 1 wherein the module is configured to receive interconnect data associated with another partition of the circuit design from the first interface.

5. The method of claim 4 wherein the module is configure to receive the interconnect data from the first interface using the at least one of the first set of wires and a serial protocol.

6. The method of claim 1 wherein the interface logic is configured to receive probe data from the first prototyping board using the at least one of the first set of wires and a serial protocol.

7. The method of claim 1 wherein the interconnection fabric is configured to route interconnect data between the plurality of prototyping boards using a packet protocol.

8. The method of claim 1 further comprising:

connecting a second prototyping board having a set of programmable logic components to the first interface using a third set of wires, the second prototyping board being described by a second plurality of board description files;

partitioning the circuit design according to the second plurality of board description files into the second prototyping board using the set of programmable logic components of the second prototyping board for emulating the circuit design; and

configuring the set of programmable logic components of the second prototyping board with a module configured to transmit data between the second prototyping board and the first interface using at least one of the third set of wires; and

configuring the set of programmable logic components of the first interface with an interconnection fabric that provides communication between the first prototyping board and the second prototyping board.

9. The method of claim 8 wherein configuring the set of programmable logic components of the first interface with the interconnection fabric comprising configuring the first interface to route interconnection data between the first prototyping board and the second prototyping board using a serial protocol.

10. The method of claim 1 further comprising:

connecting the first interface using a third set of wires to a hierarchy of interfaces configured to provide communication between one or more prototyping boards and corresponding interfaces and route interconnection data between the one or more prototyping boards.

11. A system for emulating a circuit design using a plurality of prototyping boards, the system comprising:

a first sub-system having circuitry configured to serially transmit interconnection data and probe data for each emulation cycle to each of the plurality of prototyping boards; and

a second subsystem having circuitry configured to control circuit emulation of a portion of the circuit design partitioned across the second subsystem and each of the plurality of prototyping boards associated with the first sub-system and circuitry configured to receive serially transmitted interconnection data and probe data for each emulation cycle from each of the plurality of prototyping boards.

12. The system of claim 11 wherein the interconnection data and the probe data of an emulation cycle are packed within a packet.

13. The system of claim 11 wherein the second subsystem is configured to control circuit emulation of a portion of the circuit design associated with a third sub-system, the second sub-system having circuitry configured to forward the interconnection data of an emulation cycle to the third subsystem.

14. The system of claim 11 wherein the second subsystem is configured to forward the interconnection data of an emulation cycle to a workstation.

15. The system of claim 11 wherein the second subsystem includes circuitry configured to forward the interconnection data of an emulation cycle to a third subsystem having circuitry configured to control transmissions of interconnection data and probe data for each emulation cycle.

16. The system of claim 11 wherein a first sub-system is configured to serially transmit interconnection data and probe data for each emulation cycle using a packet protocol.

17. A co-emulation and co-simulation interface comprising:

control circuitry configured to control emulation of a portion of the circuit design partitioned across the control circuitry and one or more custom prototyping boards; and

communication circuitry configured to provide communication between the control circuitry and the one or more custom prototyping boards, communication between the one or more custom prototyping boards, and communication between the control circuitry and one or more co-emulation and co-simulation interfaces.

18. The co-emulation and co-simulation interface of claim 17 wherein the communication circuitry is configured to provide the communication between the control circuitry and the one or more custom prototyping boards using a serial protocol.

19. The co-emulation and co-simulation interface of claim 17 wherein the communication circuitry is configured to forward the communication between the control circuitry and the one or more custom prototyping boards to the one or more co-emulation and co-simulation interfaces.

20. The co-emulation and co-simulation interface of claim 17 wherein the one or more co-emulation and co-simulation interfaces are configured to control the control circuitry.