Parallel-plate structure fabrication method

• US 8,950,057 B2
• Filed: 09/14/2007
• Issued: 02/10/2015
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: Valtion Teknillinen Tutkimuskeskus
• Original Assignee: Valtion Teknillinen Tutkimuskeskus
• Inventors: Riekkinen, Tommi, Mattila, Tomi
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US12/440,743
• Publication Number:
  US 20100067167A1
• Time in Patent Office: 2,706 Days
• Field of Search: 29 2535- 2542, 295/94, 295/921, 298/46, 310/320, 310/366, 333/193
• US Class Current: 29/592.1
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10N 30/06 Forming electrodes or interconnections, e.g. leads or terminals
• CPC Class Codes: H10N 30/072 by laminating or bonding of piezoelectric or electrostrictive bodies
• CPC Class Codes: H10N 30/8536 Alkaline earth metal based oxides, e.g. barium titanates
• CPC Class Codes: Y10T 29/42 Piezoelectric device making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

Claims

1. A fabrication method for parallel-plate structures,

wherein the structures have a middle layer on a first substrate and disposed between top and bottom electrode layers, and wherein the middle layer and the top and bottom electrode layers are deposited on a second substrate, the method comprising:

growing the middle layer on the first substrate first; and

depositing the bottom electrode after growing the middle layer to form a layer stack;

transferring the layer stack to the second substrate;

removing the first substrate; and

depositing the top electrode on top of the middle layer.

2. The method according to claim 1, wherein processing conditions for optimal middle layer growth are destructive for optimal electrode materials.

3. The method according to claim 1, wherein the middle layer is a ceramic material selected from the group consisting of metal oxide, metal nitride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties and combinations thereof.

4. The method according to claim 1, wherein the middle layer is selected from the group consisting of a perovskite material a piezoelectric material, or combinations thereof.

5. The method according to claim 1, wherein the middle layer is a stack of layers comprising ceramic materials selected from the group consisting of metal oxide, metal nitride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties or a combination of those, and the middle layer is perovskite material or piezoelectric material.

6. The method according to claim 1, wherein the bottom and the top electrodes at least partially comprise electrically conductive material.

7. The method according to claim 1, wherein the bottom and the top electrodes are a metal selected from the group consisting of Cu, AI, Au, Ag, Pt, and combinations thereof.

8. The method according to claim 1, wherein adhesion layers and/or diffusion barriers are applied between the bottom and top electrodes and the middle layer.

9. The method according to claim 1, wherein at least one of the bottom and the top electrodes are patterned.

10. The method according to claim 1, further comprising depositing a buffer layer on the bottom electrode and processing the buffer layer in order to facilitate wafer bonding to a second bottom substrate.

11. The method according to claim 10, further comprising bonding the buffer layer with the second substrate, and after bonding, removing the first substrate.

12. The method according to claim 11, wherein removal of the first substrate is implemented by chemical-mechanical thinning followed by plasma etching.

13. The method according to claim 10, wherein the middle layer is patterned before bonding with the second bottom substrate.

14. The method according to claim 13, wherein the middle layer is pattered for ohmic contact creation to the bottom electrode from the top electrode.

15. The method according to claim 1, wherein the growing is accomplished using electrode position to obtain thick top metal conductors.

16. The method of claim 1, wherein the middle layer is the perovsite material Ba_xSr₁₋

xTi0₃.

17. The method of claim 1, wherein the middle layer is a piezoelectric selected from the group consisting of ZnO, AIN, and combinations thereof.