Methods of making a high-density nonvolatile memory

• US 8,951,861 B2
• Filed: 02/25/2013
• Issued: 02/10/2015
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, Scott Brad, Mahajani, Maitreyee
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/776,193
• Publication Number:
  US 20130164921A1
• Time in Patent Office: 715 Days
• Field of Search: 438257-258, 438/593, 257313-316, 257/530
• US Class Current: 438/257
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.

Claims

1. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate;

forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors, each of the first plurality of semiconductor elements comprising a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer, the third heavily doped layer having a second conductivity type opposite the first conductivity type; and

forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements.

2. The method of claim 1, wherein forming the first plurality of substantially parallel, substantially coplanar conductors comprises:

depositing a first conductive layer;

patterning and etching the first conductive layer to form the first plurality of substantially parallel, substantially coplanar conductors;

depositing a first dielectric material over and between the first plurality of substantially parallel, substantially coplanar conductors; and

planarizing to expose tops of the first plurality of substantially parallel, substantially coplanar conductors separated by the first dielectric material.

3. The method of claim 2, wherein forming the first plurality of semiconductor elements comprises:

after planarizing, depositing a first semiconductor layer stack on the first dielectric material and the first plurality of substantially parallel, substantially coplanar conductors;

patterning and etching the first semiconductor layer stack to form the first plurality of semiconductor elements;

depositing a second dielectric material on and between the first plurality of semiconductor elements; and

planarizing to expose tops of the first plurality of semiconductor elements.

4. The method of claim 3, wherein depositing the first semiconductor layer stack comprises depositing polycrystalline silicon.

5. The method of claim 1, wherein each of the first plurality of semiconductor elements is pillar-shaped.

6. The method of claim 1, wherein the third heavily doped layer of each of the first plurality of semiconductor elements is doped by ion implantation.

7. The method of claim 1, wherein the first heavily doped layer of each of the first plurality of semiconductor elements is doped by in situ doping.

8. The method of claim 1, further comprising forming a second plurality of semiconductor elements above the second plurality of substantially parallel, substantially coplanar conductors.

9. The method of claim 8, further comprising forming a third plurality of substantially parallel, substantially coplanar conductors above the second plurality of semiconductor elements.

10. The method of claim 1, further comprising forming a plurality of first antifuse layers disposed between the first plurality of semiconductor elements and the second plurality of substantially parallel, substantially coplanar conductors.

11. The method of claim 10, wherein forming the first antifuse layers comprises forming oxide layers.

12. The method of claim 11, wherein forming oxide layers comprises oxidizing a portion of the third heavily doped layer of each of the first plurality of semiconductor elements.

13. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

14. The method of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.