High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices

• US 8,951,867 B2
• Filed: 12/21/2012
• Issued: 02/10/2015
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lee, Yeeheng, Chang, Hong, Kim, Jongoh, Lui, Sik, Yilmaz, Hamza, Bobde, Madhur, Calafut, Daniel, Chen, John
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/724,228
• Publication Number:
  US 20140175536A1
• Time in Patent Office: 781 Days
• Field of Search: 257/332, 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T₂ that is larger than the thickness T₁ of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method of forming a MOSFET device comprising:

a) forming a hardmask over a top surface of a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes a lightly doped drift region formed in an upper portion of the substrate, wherein the hardmask includes first, second, and third insulator layers, wherein the second layer is sandwiched between the first and third layers, wherein the third layer is between the second layer and the top surface of the semiconductor substrate, and wherein the second layer is resistant to a first etch process that etches the material of the first and third layers, and wherein the first and third layers are resistant to a second etch process that etches the material of the second layer;

b) etching the semiconductor substrate through openings in the hardmask to form a plurality of trenches in a semiconductor substrate, wherein the trenches comprise an upper portion and a lower portion;

c) lining the upper portion with an upper insulative layer of a first thickness T₁ and lining the lower portion with a lower insulative layer of a second thickness T₂, wherein T₂ is greater than T₁;

d) disposing a conductive material in the trenches to form a plurality of gate electrodes;

e) forming insulative gate caps above the gate electrodes up to at least a level of the second layer of the hardmask, wherein the insulative gate caps are made of a material that is etched by the first etch process and resistant to the second etch process;

f) etching the first layer of the hardmask and the insulative gate caps down to a level of the second layer of the hardmask using the first etch process and removing the second layer of the hardmask using the second etch process, leaving insulative gate caps aligned with the trenches protruding above a level of the third layer of the hardmask;

g) forming a body layer in a top portion of the substrate, wherein the body layer is a second conductivity type that is opposite of the first conductivity type;

h) forming a source layer of the first conductivity type in a top portion of the body layer;

i) forming a first insulative spacer layer over the gate caps and exposed portions of the third layer of the hardmask, and anisotropically etching the first insulative spacer layer leaving portions of the first insulative spacer layer along the sidewalls of the insulative gate caps as first insulative spacers;

j) forming a second insulative spacer layer over exposed portions of the third hardmask layer, the insulative gate caps and the first insulative spacers and anisotropically etching the second insulative spacer layer leaving a portion of the second insulative spacer layer along exposed sidewalls of the first insulative spacer as second insulative spacers,; and

k) forming contact openings into the semiconductor substrate for source contacts using the first and second insulative spacers as a self-aligning mask.

2. The method of claim 1, wherein forming a plurality of trenches includes forming the upper portion of the trench by etching through the openings in the hardmask and the substrate;

growing a sacrificial insulative layer along the sidewalls and bottom surface of the upper portion of the trench and forming spacers on the sacrificial insulative layer along the sidewalls;

forming the bottom portion of the trench by etching through the sacrificial insulative layer disposed on the bottom surface of the upper portion and through the substrate below the upper portion of the trench using the spacers as a mask;

growing the lower insulative layer along the sidewalls and bottom surface of the bottom portion of the trench;

removing the spacers and the sacrificial insulative layer; and

growing the upper insulative along the sidewalls of the upper portion of the trench.

3. The method of claim 1, wherein the hardmask is an oxide-nitride-oxide hardmask in which the first and third layers are made of an oxide material and the second layer is made of a nitride material.

4. The method of claim 1, wherein the first insulative spacer layer is deposited onto the surface with a CVD process.

5. The method of claim 4, wherein the first insulative spacer layer includes an oxide formed with a tetraethylorthosilicate (TEOS) gas.

6. The method of claim 1, wherein the first insulative spacer layer is made of the same material as the insulative gate cap.

7. The method of claim 1, wherein the first insulative spacer layer is resistant to the second anisotropic etch process.

8. The method of claim 7, wherein the first insulative spacers are made of the same material as the first and third layers of the hardmask.

9. The method of claim 7, wherein anisotropically etching the first insulative spacer layer further comprises etching through portions of the third layer of the hardmask that are below the portions of the first insulative spacer layer is etched away, such that portions of the top surface of the semiconductor substrate are exposed.

10. The method of claim 9, further comprising:

growing a pad insulation layer over the portions of the top surface of the semiconductor substrate that are exposed.

11. The method of claim 1, wherein the first insulative spacer layer is approximately 1,100 Å

thick.

12. The method of claim 1, wherein the first insulative spacer and the second insulative spacer are made from the same material.

13. The method of claim 12, wherein the first insulative spacer and the second insulative spacer are made from a nitride material.

14. The method of claim 1, wherein the first insulative spacers are approximately 1000 Å

thick.

15. The method of claim 1, wherein the first insulative spacer layer is made of an oxide.

16. The method of claim 15, wherein the second insulative spacer layer is made of a nitride.

17. The method of claim 15, wherein the second insulated spacer layer is disposed onto the surface with a CVD process.

18. The method of claim 15, wherein the second insulative spacer layer is approximately 300 Å

thick.

19. The method of claim 1, wherein forming the plurality of trenches in the substrate further includes forming one or more gate pickup trenches.

20. The method of claim 19, wherein disposing a conductive material in the trenches further includes disposing the conductive material in the gate pickup trenches to form gate pickup electrodes.

21. The method of claim 1, further comprising:

forming an electrostatic discharge (ESD) protection electrode above the second layer of the hard mask before it is removed by depositing a layer of conductive material over the nitride layer and by applying an ESD mask and an ESD etching process.

22. The method of claim 21, further comprising oxidizing the surface of the ESD protection electrode before removing the second layer of the hardmask.

23. The method of claim 1, further comprising:

forming one or more body clamp (BCL) structures after the second layer of the hardmask is removed, wherein the BCL structures are formed with two or more dopant implantation processes.

24. The method of claim 23, wherein a first BCL dopant implant process comprises implanting a high concentration of dopants of the second conductivity type at approximately 40 keV, and a second BCL dopant implant process comprises implanting dopants of the second conductivity type at approximately 100 keV.

25. The method of claim 23 further comprising, forming a Schottky contact with the BCL structures.

26. The method of claim 1, wherein contact openings into the semiconductor substrate for source contacts are formed sufficiently close to each other that active devices in the MOSFET device have a pitch of less than 0.6 microns.