Semiconductor device and manufacturing method thereof

• US 8,951,876 B2
• Filed: 06/20/2012
• Issued: 02/10/2015
• Est. Priority Date: 06/20/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, Ling-Chun, Wang, I-Chang, Hung, Ching-Wen
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/527,608
• Publication Number:
  US 20130341685A1
• Time in Patent Office: 965 Days
• Field of Search: 438/142, 438/197, 438/181, 438/184, 438/303, 438/304
• US Class Current: 438/303
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Claims

1. A manufacturing method for a semiconductor device, comprising steps of:

providing a substrate having at least a gate structure formed thereon, and a first spacer being formed on sidewalls of the gate structure;

performing an ion implantation to implant dopants into the substrate;

forming a disposal spacer on the sidewalls of the gate structure, the disposal spacer comprising at least a carbon-containing layer, and the carbon-containing layer directly contacting the first spacer; and

after forming the disposal spacer, then performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

2. The manufacturing method for the semiconductor device according to claim 1, wherein the carbon-containing layer is formed by a carbon source and hexachlorodisilane (Si₂Cl₆, HCD).

3. The manufacturing method for the semiconductor device according to claim 1, wherein the protecting layer comprises silicon carbon nitride based (SiCN-based) material.

4. The manufacturing method for the semiconductor device according to claim 3, wherein the SiCN-based material further comprises silicon oxycarbonitride (SiOCN).

5. The manufacturing method for the semiconductor device according to claim 1, wherein the step of forming the disposal spacer further comprises:

sequentially forming the carbon-containing layer and a silicon nitride layer blanketly covering the substrate; and

etching back the silicon nitride layer and the carbon-containing layer to form the disposal spacer.

6. The manufacturing method for the semiconductor device according to claim 5, wherein the silicon nitride layer is formed by hexachlorodisilane (Si₂Cl₆, HCD).

7. The manufacturing method for the semiconductor device according to claim 1, wherein the thermal treatment further drives-in the dopants in the substrate to form lightly-doped drains (LDDs) in the substrate simultaneously with forming the protecting layer.

8. The manufacturing method for the semiconductor device according to claim 1, further comprising:

performing an etching process to form a recess in the substrate respectively at two sides of the disposal spacer; and

performing a selective epitaxial growth (SEG) process to form an epitaxial layer in each recess.

9. The manufacturing method for the semiconductor device according to claim 8, wherein the thermal treatment is performed before the etching process.

10. The manufacturing method for the semiconductor device according to claim 8, wherein the thermal treatment is performed after the etching process and before the SEG process.

11. The manufacturing method for the semiconductor device according to claim 8, wherein the thermal treatment is performed after the SEG process.

12. The manufacturing method for the semiconductor device according to claim 8, further comprising removing the disposal spacer to expose the protecting layer after forming the epitaxial layers.

13. The manufacturing method for the semiconductor device according to claim 12, further comprising steps of:

forming a second spacer on the protecting layer; and

forming a source/drain respectively in the epitaxial layers at two sides of the second spacer.

14. The manufacturing method for the semiconductor device according to claim 1, wherein the thermal treatment comprises a spike rapid thermal process (spike RTP).

15. The manufacturing method for the semiconductor device according to claim 1, wherein the thermal treatment comprises a process temperature between 850°

C. and 1000°

C.

16. A manufacturing method for a semiconductor device, comprising steps of:

providing a substrate having at least a gate structure formed thereon, and a first spacer being formed on sidewalls of the gate structure;

forming at least a carbon-containing layer on the substrate, and the carbon-containing layer directly contacting the first spacer;

performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer; and

performing an etching back process to form a disposal spacer on the sidewalls of the gate structure.

17. The manufacturing method for the semiconductor device according to claim 16, wherein the carbon-containing layer is formed by a carbon source gas and hexachlorodisilane (Si₂Cl₆, HCD).

18. The manufacturing method for the semiconductor device according to claim 16, wherein the protecting layer comprises silicon carbon nitride based (SiCN-based) material.

19. The manufacturing method for the semiconductor device according to claim 18, wherein the SiCN-based material further comprises silicon oxycarbonitride (SiOCN).

20. The manufacturing method for the semiconductor device according to claim 16, further comprising forming a silicon nitride layer on the carbon-containing layer, and the silicon nitride layer is formed by hexachlorodisilane (Si₂Cl₆, HCD).

21. The manufacturing method for the semiconductor device according to claim 16, further comprising performing an ion implantation to implant dopants into the substrate.

22. The manufacturing method for the semiconductor device according to claim 21, wherein the thermal treatment further drives-in the dopants in the substrate to form lightly-doped drains in the substrate simultaneously with forming the protecting layer.

23. The manufacturing method for the semiconductor device according to claim 21, wherein the thermal treatment is performed after the ion implantation.

24. The manufacturing method for the semiconductor device according to claim 21, wherein the carbon-containing layer is formed after performing the ion implantation.

25. The manufacturing method for the semiconductor device according to claim 21, wherein the carbon-containing layer is formed before performing the ion implantation.