Graded dielectric structures

• US 8,951,903 B2
• Filed: 02/03/2012
• Issued: 02/10/2015
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gealy, Dan, Bhat, Vishwanath, Srividya, Cancheepuram V., Rocklein, M. Noel
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US13/366,025
• Publication Number:
  US 20120202358A1
• Time in Patent Office: 1,103 Days
• Field of Search: 438/591, 438/785, 438/786, 257/E21.625
• US Class Current: 438/591
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Claims

1. A method comprising:

controlling formation of a dielectric structure to form a graded dielectric in an integrated circuit such that the dielectric structure has a structure profile that varies across the dielectric structure;

forming, in the dielectric structure, a crystalline region having a composition consisting of a plurality of elements including a metal, using a type of precursor containing the metal, the composition being a dielectric composition; and

forming, in the dielectric structure, an amorphous region consisting of the same elements as the crystalline region, the amorphous region formed by using a type of precursor containing the metal being formed in the amorphous region different from the type of precursor containing the metal used to form the crystalline region.

2. The method of claim 1, wherein controlling formation of the dielectric structure includes forming a crystalline dielectric region interior to the graded dielectric.

3. The method of claim 2, wherein controlling formation of the dielectric structure includes forming an amorphous dielectric region at an interface of the graded dielectric with another material.

4. The method of claim 3, wherein forming the amorphous dielectric region at the interface of the graded dielectric includes forming the amorphous dielectric region contacting a conductive material.

5. The method of claim 4, wherein forming the amorphous dielectric region contacting the conductive material includes forming the amorphous dielectric region contacting titanium nitride.

6. The method of claim 4, wherein forming the amorphous dielectric region contacting the conductive material includes forming the amorphous dielectric region contacting tantalum nitride.

7. The method of claim 2, wherein controlling formation of the dielectric structure includes forming amorphous dielectric regions at interfaces at opposing sides of the graded dielectric.

8. The method of claim 7, wherein forming one of the amorphous dielectric regions includes forming a silicon-rich metal silicon oxide.

9. The method of claim 8, wherein forming the silicon-rich metal silicon oxide includes forming a metal silicon oxide with an atomic percentage of silicon in the metal silicon oxide being greater than an atomic percentage of the metal in the metal silicon oxide.

10. The method of claim 8, wherein forming the crystalline dielectric region interior to the graded dielectric includes forming substantially a metal oxide whose compound has the metal of the silicon-rich metal silicon oxide.

11. The method of claim 8, wherein forming the silicon-rich metal silicon oxide includes forming a silicon-rich hafnium silicon oxide.

12. The method of claim 11, wherein forming the silicon-rich hafnium silicon oxide includes forming a silicon-rich hafnium silicate.

13. The method of claim 8, wherein forming the silicon-rich metal silicon oxide includes forming a silicon-rich zirconium silicon oxide.

14. The method of claim 13, wherein forming the silicon-rich zirconium silicon oxide includes forming a silicon-rich zirconium silicate.

24. The method of claim 1, wherein controlling formation of the dielectric structure includes forming a region of crystal grains such that the region of crystal grains is arranged as a wave of crystallinity in which crystal grain size varies.

25. The method of claim 1, wherein controlling formation of the dielectric structure includes controlling crystallinity of the dielectric structure by controlling amounts of different materials in forming the dielectric structure.

26. The method of claim 1, wherein controlling formation of the dielectric structure includes forming an amorphous region with controlled nanocrystalline content within the amorphous region.

27. The method of claim 1, wherein controlling formation of the dielectric structure includes forming the amorphous region and the crystalline region using a monolayer or partial monolayer sequencing process.

28. The method of claim 1, wherein forming the amorphous region and forming the crystalline region includes using a chloride precursor to form the crystalline region and using an amide precursor to form the amorphous region.

29. The method of claim 1, wherein the amorphous region includes hafnium oxide region and the crystalline region includes hafnium oxide.

15. A method comprising:

controlling a structure profile of a dielectric structure that varies across the dielectric structure to form a graded dielectric in an integrated circuit, wherein controlling the structure profile includes;

forming, using a monolayer or partial monolayer sequencing process, a crystalline dielectric region having a composition consisting of a plurality of elements including a metal, using a type of precursor containing the metal, the composition being a dielectric composition;

forming a wave of crystallinity in which long range order varies across the wave of crystallinity; and

forming, using the monolayer or partial monolayer sequencing process, an amorphous dielectric region disposed on the crystalline dielectric region, the amorphous dielectric region consisting of the same elements as the crystalline dielectric region, the amorphous dielectric region formed by using a type of precursor containing the metal being formed in the amorphous region different from the type of precursor containing the metal used to form the crystalline dielectric region.

16. The method of claim 15, wherein forming the amorphous dielectric region includes forming the amorphous dielectric region at an interface of the graded dielectric with another material.

17. The method of claim 16, wherein forming the amorphous dielectric region at the interface of the graded dielectric includes forming the amorphous dielectric region contacting a conductive material.

18. The method of claim 15, wherein forming the crystalline dielectric region includes forming a metal oxide containing a plurality of metal species.

19. The method of claim 18, wherein forming the metal oxide containing the plurality of metal species includes forming a metal oxide with hafnium and aluminum.

20. The method of claim 18, wherein forming the metal oxide containing the plurality of metal species includes forming a metal oxide with hafnium and silicon.

21. The method of claim 18, wherein forming the metal oxide containing the plurality of metal species includes forming a metal oxide with zirconium and aluminum.

22. The method of claim 18, wherein forming the metal oxide containing the plurality of metal species includes forming a metal oxide with zirconium and silicon.

23. The method of claim 18, wherein forming the crystalline dielectric region includes forming a metal oxynitride.