Semiconductor device and manufacturing method thereof

• US 8,952,377 B2
• Filed: 06/20/2012
• Issued: 02/10/2015
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Shinohara, Satoshi
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/527,882
• Publication Number:
  US 20130009219A1
• Time in Patent Office: 965 Days
• Field of Search: 257/43, 257/59, 257/72
• US Class Current: 257/43
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

an oxide semiconductor stacked layer over the gate insulating film comprising;

a first oxide semiconductor layer; and

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a source electrode and a drain electrode over the oxide semiconductor stacked layer,

wherein an energy gap of the first oxide semiconductor layer and an energy gap of the second oxide semiconductor layer are different from each other, and

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

2. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer covers a top and side surfaces of the first oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor stacked layer includes a low-resistance region including a dopant.

4. The semiconductor device according claim 1,

wherein the oxide semiconductor stacked layer comprises a mixed region between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first element,

wherein the second oxide semiconductor layer comprises a second element, and

wherein the mixed region comprises the first element and the second element.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor stacked layer comprises a third oxide semiconductor layer over the second oxide semiconductor layer;

and

wherein the energy gap of the second oxide semiconductor layer is smaller than an energy gap of the third oxide semiconductor layer.

6. The semiconductor device according to claim 5,

wherein the third oxide semiconductor layer covers a side surface of the first oxide semiconductor layer and a top and side surfaces of the second oxide semiconductor layer.

7. A semiconductor device comprising:

a gate electrode;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode over the gate insulating film; and

an oxide semiconductor stacked layer over the source electrode and the drain electrode comprising;

a first oxide semiconductor layer; and

a second oxide semiconductor layer over the first oxide semiconductor layer,

wherein an energy gap of the first oxide semiconductor layer and an energy gap of the second oxide semiconductor layer are different from each other, and

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

8. The semiconductor device according to claim 7,

wherein the second oxide semiconductor layer covers a top and side surfaces of the first oxide semiconductor layer.

9. The semiconductor device according to claim 7, wherein the oxide semiconductor stacked layer includes a low-resistance region including a dopant.

10. The semiconductor device according claim 7,

wherein the oxide semiconductor stacked layer comprises a mixed region between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first element,

wherein the second oxide semiconductor layer comprises a second element, and

wherein the mixed region comprises the first element and the second element.

11. The semiconductor device according to claim 7,

wherein the oxide semiconductor stacked layer comprises a third oxide semiconductor layer over the second oxide semiconductor layer,

wherein the energy gap of the second oxide semiconductor layer is smaller than an energy gap of the third oxide semiconductor layer.

12. The semiconductor device according to claim 11,

wherein the third oxide semiconductor layer covers a side surface of the first oxide semiconductor layer and a top and side surfaces of the second oxide semiconductor layer.

13. A semiconductor device, comprising:

a gate electrode;

a gate insulating film over the gate electrode;

an oxide semiconductor stacked layer comprising;

a first oxide semiconductor layer; and

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a source electrode and a drain electrode,

wherein the oxide semiconductor stacked layer and the source and drain electrodes are positioned over the gate insulating film,

wherein the oxide semiconductor stacked layer and the source and drain electrodes overlap each other, and

wherein an energy gap of the first oxide semiconductor layer and an energy gap of the second oxide semiconductor layer are different from each other, and

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

14. The semiconductor device, according to claim 13,

wherein the second oxide semiconductor layer covers a top and side surfaces of the first oxide semiconductor layer.

15. The semiconductor device, according to claim 13,

wherein the oxide semiconductor stacked layer includes a low-resistance region including a dopant.

16. The semiconductor device, according to claim 13,

wherein the oxide semiconductor stacked layer comprises a mixed region between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first element,

wherein the second oxide semiconductor layer comprises a second element, and

wherein the mixed region comprises the first element and the second element.

17. The semiconductor device, according to claim 13,

wherein the oxide semiconductor stacked layer comprises a third oxide semiconductor layer, and

wherein the energy gap of the second oxide semiconductor layer is smaller than an energy gap of the third oxide semiconductor layer.

18. The semiconductor device, according to claim 17,

wherein the third oxide semiconductor layer covers a side surface of the first oxide semiconductor layer and a top and side surfaces of the second oxide semiconductor layer.