Semiconductor device and method for manufacturing semiconductor device

• US 8,952,430 B2
• Filed: 06/02/2011
• Issued: 02/10/2015
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Takaya, Hidefumi, Matsuki, Hideo, Suzuki, Naohiro, Ishikawa, Tsuyoshi
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US13/703,284
• Publication Number:
  US 20130075760A1
• Time in Patent Office: 1,349 Days
• Field of Search: 257/288, 257/329, 257/330, 257/331, 257/332, 257/334, 257/341, 257/E29.257, 257/E21.334, 257/E29.255
• US Class Current: 257/288
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of SiC including a cell area and a termination area that surrounds the cell area;

wherein

the cell area is provided with a plurality of main trenches,

the termination area is provided with a plurality of termination trenches surrounding the cell area,

the plurality of termination trenches comprise a first termination trench, which is disposed at an innermost circumference, and one or more second termination trenches,

the one or more second termination trenches are disposed on an outer circumference side of the first termination trench,

in an inner region of the first termination trench, a first conductive type body region is disposed on a surface of a second conductive type drift region,

each of the plurality of main trenches penetrates the body region from a surface of the semiconductor substrate and reaches the drift region,

a gate electrode is provided within each of the plurality of main trenches,

a bottom surface of each of the plurality of main trenches is covered with a second insulating layer,

the first termination trench penetrates the body region from the surface of the semiconductor substrate and reaches the drift region,

sidewalls and a bottom surface of the first termination trench are covered with a first insulating layer,

the first insulating layer includes at least a covering portion disposed on the bottom surface of the first termination trench,

at least a part of a surface of the covering portion is covered with a conductive layer,

a thickness of a portion covering the bottom surface of the first insulating layer is thinner than a thickness of the second insulating layer,

a depth of the plurality of main trenches is identical to a depth of the first termination trench,

each second termination trench surrounds the outer circumference of the first termination trench, is narrower than the first termination trench, penetrates the body region from a surface of the body region, and reaches the drift region,

a particular potential is applied to the conductive layer at least during when no on-potential is applied to the gate electrodes, and

the particular potential is equal to a potential applied to the gate electrodes or a source electrode when no on-potential is applied to the gate electrodes.

2. The semiconductor device as in claim 1, further comprising a semiconductor region and a contact region, wherein the semiconductor region is formed in a region exposed at the surface of the semiconductor substrate, is a second conductive type region, is disposed adjacent to the main trenches, and is separated from the drift region by the body region, the contact region is formed at a surface of the body region, and electrically connects with the semiconductor region, and no contact region is formed at an outer region of a region surrounded by the first termination trench.

3. The semiconductor device as in claim 1, wherein a depth of the first termination trench is identical to a depth of the second termination trenches.

4. The semiconductor device as in claim 2, wherein a first distance between the first termination trench and a termination trench adjacent to the first termination trench is smaller than a second distance between the first termination trench and a main trench adjacent to the first termination trench.

5. The semiconductor device as in claim 1, wherein

a third insulating layer covers an upper portion of each main trench,

the conductive layer includes aluminum,

the conductive layer continuously covers a surface of the first insulating layer covering the bottom surface and the sidewalls of the first termination trench, a surface of the body region being present in the inner region of the first termination trench, and a surface of the third insulating layer covering the main trenches, and

a potential being equal to a potential applied to the source electrode is applied to the conductive layer.

10. The semiconductor device as in claim 1, wherein

a third insulating layer covers an upper portion of each main trench,

the conductive layer includes aluminum,

the conductive layer is provided with a first end portion,

the conductive layer is disposed in an inner region of the first end portion,

when the semiconductor device is observed from vertically above the semiconductor substrate, the first end portion is positioned on an inner circumference of a surface position of the first insulating layer covering an outer circumference side of the sidewalls of the first termination trench,

the conductive layer continuously covers a surface of the first insulating layer covering the bottom surface and sidewalls of the first termination trench, a surface of the body region being present in inner region of the first termination trench, and a surface of the third insulating layer covering the main trenches,

a potential being equal to a potential applied to the source electrode is applied to the conductive layer, and

a fourth insulating layer covers a surface of the first insulating layer covering the sidewalls of the first termination trench, a surface and sidewalls of the conductive layer covering the surface of the first insulating layer, and a surface of the first insulating layer covering the bottom surface of the first termination trench at an outer region of the first end portion.

11. The semiconductor device as in claim 10, wherein

a distance between a surface of the first insulating layer covering an outer circumference side of the sidewalls of the first termination trench and the first end portion of the conductive layer is a distance in which a region between a surface of the first insulating layer covering the outer circumference side of the sidewalls of the first termination trench and the first end portion of the conductive layer is filled without any voids by the fourth insulating layer covering the conductive layer.

12. The semiconductor device as in claim 1, wherein

a second end portion of the conductive layer is formed at the surface of the semiconductor substrate and near an opening portion of the first termination trench, and

when the semiconductor device is observed from vertically above the semiconductor substrate, the second end portion of the conductive layer disposed on an outer region of the first termination trench is positioned on an inner circumference of an outer circumference side of the sidewalls of the first termination trench.

13. The semiconductor device as in claim 1, wherein

a first conductive type first diffusion layer is formed on at least a part of the drift region disposed on the bottom surface of the first termination trench.

14. The semiconductor device as in claim 1, further comprising a plurality of the second termination trenches.

15. The semiconductor device as in claim 13, wherein the first diffusion layer comprises a third end portion,

the first diffusion layer is formed at an inner region of the third end portion, and

when the semiconductor device is observed from vertically above the semiconductor substrate, the third end portion is positioned on an outer circumference side of the outer circumference side of the sidewalls of the first termination trench.

16. The semiconductor device as in claim 13, wherein

the first diffusion layer comprises a fourth end portion,

the first diffusion layer is formed at an outer region of the fourth end portion, and

when the semiconductor device is observed from vertically above the semiconductor substrate, the fourth end portion is positioned on an outer circumference side of the inner circumference side of the sidewalls of the first termination trench.

6. A semiconductor device comprising:

a semiconductor substrate of SiC including a cell area and a termination area that surrounds the cell area;

wherein

the cell area is provided with a plurality of main trenches,

the termination area is provided with one or more termination trenches surrounding the cell area,

the one or more termination trenches comprise a first termination trench, which is disposed at an innermost circumference,

in an inner region of the first termination trench, a first conductive type body region is disposed on a surface of a second conductive type drift region,

each main trench penetrates the body region from a surface of the semiconductor substrate and reaches the drift region,

a gate electrode is provided within each main trench,

a bottom surface of each main trench is covered with a second insulating layer,

the first termination trench penetrates the body region from the surface of the semiconductor substrate and reaches the drift region,

sidewalls and a bottom surface of the first termination trench are covered with a first insulating layer,

the first insulating layer includes at least a covering portion disposed on the bottom surface of the first termination trench,

at least a part of a surface of the covering portion is covered with a conductive layer,

a thickness of a portion covering the bottom surface of the first insulating layer is thinner than a thickness of the second insulating layer,

a depth of the plurality of main trenches is identical to a depth of the first termination trench

a particular potential is applied to the conductive layer at least during when no on-potential is applied to the gate electrodes, and

the particular potential is equal to a potential applied to the gate electrodes or a source electrode when no on-potential is applied to the gate electrodes,

wherein a thickness of the first insulating layer covering an outer circumference side of the sidewalls of the first termination trench is thicker than a thickness of the first insulating layer covering an inner circumference side of the sidewalls and the bottom surface of the first termination trench.

7. A semiconductor device comprising:

a semiconductor substrate of SiC including a cell area and a termination area that surrounds the cell area;

wherein

the cell area is provided with a plurality of main trenches,

the termination area is provided with one or more termination trenches surrounding the cell area,

the one or more termination trenches comprise a first termination trench, which is disposed at an innermost circumference,

in an inner region of the first termination trench, a first conductive type body region is disposed on a surface of a second conductive type drift region,

each main trench penetrates the body region from a surface of the semiconductor substrate and reaches the drift region,

a gate electrode is provided within each main trench,

a bottom surface of each main trench is covered with a second insulating layer,

the first termination trench penetrates the body region from the surface of the semiconductor substrate and reaches the drift region,

sidewalls and a bottom surface of the first termination trench are covered with a first insulating layer,

the first insulating layer includes at least a covering portion disposed on the bottom surface of the first termination trench,

at least a part of a surface of the covering portion is covered with a conductive layer,

a thickness of a portion covering the bottom surface of the first insulating layer is thinner than a thickness of the second insulating layer,

a depth of the plurality of main trenches is identical to a depth of the first termination trench,

a particular potential is applied to the conductive layer at least during when no on-potential is applied to the gate electrodes, and

the particular potential is equal to a potential applied to the gate electrodes or a source electrode when no on-potential is applied to the gate electrodes,

wherein

the first insulating layer comprises a lower layer insulating layer and an upper layer insulating layer,

the lower layer insulating layer covers the sidewalls and the bottom surface of the first termination trench,

the conductive layer is provided with a first end portion,

the conductive layer is formed at an inner region of the first end portion,

when the semiconductor device is observed from vertically above the semiconductor substrate, the first end portion is positioned on an inner circumference of a surface position of the first insulating layer covering an outer circumference side of the sidewalls of the first termination trench,

the upper layer insulating layer covers a surface of the lower layer insulating layer covering the sidewalls of the first termination trench, a surface and sidewalls of the conductive layer covering the surface of the lower layer insulating layer, and a surface of the lower layer insulating layer covering the bottom surface of the first termination trench at an outer region of the first end portion.

8. The semiconductor device as in claim 7, wherein

a distance between a surface of the lower layer insulating layer covering an outer circumference side of the sidewalls of the first termination trench and the first end portion of the conductive layer is a distance in which a region between the surface of the lower layer insulating layer covering the outer circumference side of the sidewalls of the first termination trench and the first end portion of the conductive layer is filled without any voids by the upper layer insulating layer covering the conductive layer.

9. The semiconductor device as in claim 8, wherein

the distance between the surface of the lower layer insulating layer covering the outer circumference side of the sidewalls of the first termination trench and the first end portion of the conductive layer is twice a thickness of the upper layer insulating layer covering the conductive layer.