Method of fabricating backside-illuminated image sensor

• US 8,952,474 B2
• Filed: 10/04/2012
• Issued: 02/10/2015
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Kuan-Chieh, Yaung, Dun-Nian, Wu, Chih-Jen, Huang, Chen-Ming
• Primary Examiner(s): MONTALVO, EVA Y
• Application Number:
  US13/644,657
• Publication Number:
  US 20130093036A1
• Time in Patent Office: 859 Days
• Field of Search: 257/444, 257/447, 257/433, 257/432, 257/E27.133, 438/70, 438/66
• US Class Current: 257/434
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 31/0232 : Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H05K 2201/10151 : Sensor
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor.

Claims

1. A method for forming a semiconductor device, the method comprising:

providing a device substrate having a frontside and a backside defined thereupon, the backside opposite the frontside, the device substrate further having a plurality of pixels formed at the frontside;

forming a color filter layer and one or more microlenses on the backside of the device substrate;

forming a dam structure on the backside of the device substrate;

coupling a backside substrate to the dam structure, wherein the backside substrate is coupled to the dam structure to define a cavity surrounding the color filter layer and the one or more microlenses;

prior to the forming of the color filter layer and the one or more microlenses and prior to the forming of the dam structure;

forming an interconnect structure disposed over and coupled to the frontside of the device substrate; and

coupling a glass substrate to the interconnect structure, wherein the forming of the color filter layer and the one or more microlenses, the forming of the dam structure, and the coupling of the backside substrate are performed using the glass substrate; and

forming a redistribution layer disposed over and electrically coupled to the interconnect structure;

wherein the forming of the redistribution layer is performed prior to the coupling of the glass substrate, and wherein the coupling of the glass substrate releasably couples the glass substrate to the redistribution layer.

2. The method of claim 1, further comprising decoupling the glass substrate from the redistribution layer at a temperature greater than a temperature used for bonding the glass substrate.

3. The method of claim 1, further comprising dicing the device substrate to form a chip that includes the semiconductor device.

4. A method for forming a semiconductor device, the method comprising:

providing a device substrate having a frontside and a backside, wherein a plurality of pixels are formed at the frontside;

forming an interconnect structure over the pixels, the interconnect structure including a bonding pad;

bonding a glass substrate to the interconnect structure;

forming a redistribution layer over the glass substrate;

etching a portion of the glass substrate and the interconnect structure to expose the bonding pad, the etching defining an etched region;

depositing a conductive material within the etched region, the conductive material electrically coupled to the bonding pad.

5. The method of claim 4, further comprising:

forming a passivation layer over the conductive material to define another bonding pad electrically coupled to the bonding pad of the interconnect structure.

6. The method of claim 4, further comprising thinning and processing the backside of the device substrate using the glass substrate.

7. The method of claim 6, wherein the thinning and processing of the backside of the device substrate includes:

performing one or more of grinding, etching, and chemical-mechanical planarization on the backside of the device substrate;

thereafter forming a color filter layer and one or more microlenses on the backside of the device substrate;

forming a dam structure on the backside of the device substrate; and

coupling a backside substrate to the dam structure, wherein the backside substrate is coupled to the dam structure to define a cavity surrounding the color filter layer and the one or more microlenses.

8. A method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate includes;

a frontside surface;

a backside surface located opposite the frontside;

a plurality of pixels formed at the frontside surface; and

forming an interconnect structure disposed over and electrically coupled to the frontside surface of the semiconductor substrate; and

forming a redistribution layer disposed over and electrically coupled to the interconnect structure; and

releasably coupling a second substrate to the redistribution layer, wherein the coupling of the second substrate to the redistribution layer includes applying an adhesive on the redistribution layer such that the adhesive is disposed between a first redistribution feature and a second redistribution feature.

9. The method of claim 8, further comprising thinning the semiconductor substrate from the backside surface using the second substrate.

10. The method of claim 9, further comprising forming a planarization layer on the backside surface of the thinned semiconductor substrate using the second substrate.

11. The method of claim 9, further comprising forming a color filter layer on the backside surface of the thinned semiconductor substrate using the second substrate.

12. The method of claim 11, further comprising forming a microlense on the color filter layer using the second substrate.

13. The method of claim 12, further comprising:

forming a dam structure on the backside surface of the thinned semiconductor substrate such that the dam structure extends to a height greater than a top surface of the microlense; and

coupling a third substrate to the dam structure such that the third structure covers the microlense.

14. The method of claim 13, further comprising filling a chamber formed by the third substrate with an epoxy material.

15. The method of claim 13, further comprising decoupling the second substrate from the redistribution layer after the coupling of the third substrate to the dam structure.

16. The method of claim 15, wherein the decoupling of the second substrate includes heating the second substrate to a temperature greater than a bonding temperature of the adhesive used to couple the second substrate.

17. The method of claim 15, further comprising reusing the second substrate to fabricate another semiconductor device after the decoupling of the second substrate from the redistribution layer.

18. The method of claim 8, wherein the adhesive is disposed on a top surface and two side surfaces of each of the first redistribution feature and the second redistribution feature.

19. The method of claim 8, wherein the adhesive physically contacts a side surface of each of the first redistribution feature and the second redistribution feature.

20. The method of claim 15, wherein the bonding temperature of the adhesive used to couple the second substrate ranges between about 200°

C. and about 300°

C.