Devices and methods for 2.5D interposers

• US 8,952,533 B2
• Filed: 05/17/2013
• Issued: 02/10/2015
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Mohammed, Anwar A., Liu, Weifeng, Niu, Rui
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US13/897,156
• Publication Number:
  US 20140070406A1
• Time in Patent Office: 634 Days
• Field of Search: 257/737, 257/773, 257/685, 257/686, 257/723, 257/738, 257/734, 257/777, 257/778, 257/779, 257/780, 257/782
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.

Claims

1. A semiconductor package comprising:

an organic substrate;

two or more semiconductor dies; and

an interposer positioned between the organic substrate and the two or more semiconductor dies in a 2.5 D semiconductor packaging configuration, the interposer comprising a re-distribution layer comprising one or more polyimide-based dielectric layers, wherein the one or more polyimide-based dielectric layers are composed primarily of a polyimide (PI) compound.

2. The semiconductor package of claim 1, wherein the interposer comprises an inorganic core having a coefficient of thermal expansion (CTE) that is at least five parts per million less than the organic substrate, and

wherein the re-distribution layer further comprises one or more conductive layers coupled to the organic substrate via a conductive interconnection.

3. The semiconductor package of claim 2, wherein the interposer comprises a silicon-based core.

4. The semiconductor package of claim 2, wherein the interposer comprises a glass core.

5. The semiconductor package of claim 2, wherein the conductive interconnection comprises a controlled collapse chip connection (C4) bump.

6. The semiconductor package of claim 1, wherein the interposer comprises an organic core having a coefficient of thermal expansion (CTE) that is at least five parts per million greater than that of the two or more semiconductor dies, and

wherein the re-distribution layer further comprises a conductive layer that is coupled to the two or more semiconductor dies via a conductive interconnection.

7. The semiconductor package of claim 6, wherein the conductive interconnection comprises a controlled collapse chip connection (C4) bump.

8. The semiconductor package of claim 1, wherein the two or more semiconductor dies are affixed to an upper face of the interposer, the two or more semiconductor dies being positioned laterally with respect to one another.

9. A semiconductor package comprising:

an interposer;

a first semiconductor die mounted to an upper face of the interposer; and

a second semiconductor die affixed to the upper face of the interposer, the second semiconductor die being positioned adjacently to the first semiconductor die in accordance with a 2.5 D semiconductor packaging configuration,

wherein the second semiconductor die is taller than the first semiconductor die,

wherein the upper-most faces of both the first semiconductor die and the second semiconductor die directly contact a planar face of a common heat sink, and

wherein the first semiconductor die is mounted higher than the second semiconductor die such that the uppermost faces of both semiconductor dies directly contact the planar face of the common heat sink.

10. The semiconductor package of claim 9, wherein a height of the second semiconductor die exceeds a height of the first semiconductor die by at least 50 microns.

11. The semiconductor package of claim 9, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 10 microns.

12. The semiconductor package of claim 9, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 5 microns.

13. The semiconductor package of claim 9, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 1 micron.

14. The semiconductor package of claim 9, further comprising:

a first set of conductive interconnections bonding the first semiconductor die to the upper face of the interposer; and

a second set of conductive interconnections bonding the first semiconductor die to the upper face of the interposer,

wherein a height of the first set of conductive interconnections exceeds a height of the second set of conductive interconnections.

15. The semiconductor package of claim 14, wherein the first set of conductive interconnections comprises a first set of controlled collapse chip connection (C4) bumps.

16. The semiconductor package of claim 15, wherein the second set of conductive interconnections comprises a second set of C4 bumps.

17. The semiconductor package of claim 16, wherein C4 bumps in the second set of C4 bumps have a smaller diameter than C4 bumps in the first set of C4 bumps.

18. The semiconductor package of claim 14, wherein the first set of conductive interconnections comprises a first set of copper pillars.

19. The semiconductor package of claim 18, wherein the second set of conductive interconnections comprises a second set of copper pillars.

20. The semiconductor package of claim 19, wherein copper pillars in the second set of copper pillars are shorter than copper pillars in the first set of copper pillars.

21. A semiconductor package comprising:

a multi-tiered interposer comprising an upper-interposer face, the upper-interposer face having a first tier and a second tier;

a first semiconductor die mounted to the first tier of the upper-interposer face; and

a second semiconductor die mounted to the second tier of the upper-interposer face, the second semiconductor die being positioned laterally adjacent to the first semiconductor die in accordance with a 2.5 D semiconductor packaging configuration,

wherein a height of the second semiconductor die exceeds a height of the first semiconductor die,

wherein upper-most faces of both the first semiconductor die and the second semiconductor die directly contact a planar face of a common heat sink, and

wherein the first tier of the upper-interposer face is raised in relation to second tier of the upper-interposer face such that the uppermost faces of both semiconductor dies directly contact the planar face of the common heat sink.

22. The semiconductor package of claim 21, wherein a height of the second semiconductor die exceeds a height of the first semiconductor die by at least 50 microns.

23. The semiconductor package of claim 21, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 10 microns.

24. The semiconductor package of claim 21, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 5 microns.

25. The semiconductor package of claim 21, wherein a vertical separation between uppermost points of the first semiconductor die and second semiconductor die is less than 1 micron.