Method and apparatus for die testing

• US 8,952,713 B1
• Filed: 02/08/2012
• Issued: 02/10/2015
• Est. Priority Date: 02/08/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Dastidar, Jayabrata Ghosh, Beni, Aman Aflaki, Kasnavi, Zunhang Yu
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): McDonnough, Courtney
• Application Number:
  US13/369,224
• Time in Patent Office: 1,098 Days
• Field of Search: None
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.

Claims

1. A device tester comprising:

a substrate coupled to the probe card, wherein the substrate comprises a plurality of layers for routing a signal; and

an integrated circuit coupled to the substrate, wherein the integrated circuit receives an input signal from a testing apparatus, and wherein said integrated circuit transmits the received input signal to a device under test via signal probe of said substrate, wherein the signal probe receives a test signal from the device under test in response to transmission of the input signal to said device under test, wherein the integrated circuit amplifies the test signal and transmits the amplified test signal to the testing apparatus, wherein the integrated circuit comprises a voltage level shifting circuit, with a unity gain first buffer configured to transfer a unity gain, non-level-translated version of the test signal into the voltage level shifting circuit.

2. The device tester of claim 1, further comprising a probe card coupled to the substrate, wherein the probe card comprises a plurality of electrically conductive paths.

3. The device tester of claim 1, wherein the device under test transmits the test signal through micro bumps disposed on a surface of the device under test.

4. The device tester of claim 2, wherein the probe card is coupled to a power probe operable to provide power to the device under test.

5. The device tester of claim 1, wherein the amplification is in response to comparing a level of the test signal to a minimum threshold value.

6. The device tester of claim 1, wherein the voltage level shifting circuit includes the unity gain first buffer that receives the test signal and a second buffer that transmits the amplified test signal from the voltage level circuit to the testing apparatus.

7. The device tester of claim 6, wherein the unity gain first buffer has a smaller voltage capacity than the second buffer.

8. A device tester comprising:

an integrated circuit disposed on a multi-layer semiconductor substrate, the integrated circuit electrically coupled to a testing apparatus and a device under test, the integrated circuit configured to propagate electrical signals between the testing apparatus and the device under test, wherein the integrated circuit amplifies a voltage level of a response received from the device under test, the integrated circuit including a first unity gain buffer configured to receive the voltage level of the response from the device under test, the integrated circuit including a voltage level shifting circuit configured to receive an output of the first unity gain buffer and configured to amplify the voltage level of the response from the device under test, wherein the response generated by the device under test is based on a test signal transmitted to the device under test, and wherein said response is transmitted to the testing apparatus through the integrated circuit.

9. The device tester of claim 8 comprising a signal probe that transmits the test signal from the integrated circuit to the device under test.

10. The device tester of claim 9, wherein the signal probe couples to micro bumps of the device under test.

11. The device tester of claim 8 comprising a power probe coupled to the substrate and configured to provide power to the device under test.

12. The device tester of claim 8, wherein the substrate comprises a plurality of electrically conductive paths.

13. The device tester of claim 8, further comprising a probe card, wherein the probe card further comprises a decoupling capacitor.

14. The device tester of claim 8, wherein the voltage level shifting circuit includes a second buffer that transmits the amplified voltage level response.

15. The device tester of claim 14, wherein the first unity gain buffer has a voltage capacity that is less than a voltage capacity of the second buffer.

16. A method for testing a device under test, the method comprising:

receiving an input signal from a testing apparatus;

transmitting the input signal to a device under test through an integrated circuit, the integrated circuit included on a substrate coupled to a probe card;

in response to said transmitting, receiving a response from the device under test;

buffering the response from the device under test through a unity gain buffer;

level shifting an output of the unity gain buffer;

amplifying a voltage level of the level-shifted response through amplification circuitry of the integrated circuit in response to comparing the voltage level of the response to a minimum voltage level; and

transmitting the amplified response to the testing apparatus.

17. The method as in claim 16 further comprising receiving the response from the device under test through a micro bump interconnection.